Jan 7, 2021

[paper] Generalized EKV Charge-based MOSFET Model

A Generalized EKV Charge-based MOSFET Model Including Oxide and Interface Traps
Chun-Min Zhanga,  Farzan Jazaeria,  Giulio Borghellob,  Serena Mattiazzoc,  Andrea Baschirottod
and Christian Enza
Available online 7 January 2021, 107951
Open Access under a Creative Commons License
DOI: 10.1016/j.sse.2020.107951

a Integrated Circuits Laboratory (ICLAB), École Polytechnique Fédérale de Lausanne (EPFL), Neuchâtel 2000, Switzerland
b Department of Experimental Physics, CERN, Geneva 1211, Switzerland
c Department of Information Engineering, INFN Padova and University of Padova, Padova 35131, Italy
d Microelectronic Group, INFN Milano-Bicocca and University of Milano-Bicocca, Milano 20126, Italy

Abstract: This paper presents a generalized charge-based EKV MOSFET model that includes the effects of trapped charges in the bulk oxide and at the silicon/oxide interface. It is shown that in the presence of oxide- and interface-trapped charges, the mobile charge density can still be linearized but with respect to both the surface potential and the channel voltage. This enables us to derive closed-form expressions for the mobile charge density and the drain current. These simple formulations demonstrate the effects of charge trapping on MOSFET characteristics and crucial device parameters. The proposed charge-based analytical model, including the effect of velocity saturation, is successfully validated through measurements performed on devices from a 28nm bulk CMOS technology. Ultrahigh total ionizing doses up to 1 Grad (SiO2) are applied to generate oxide-trapped charges and activate the passivated interface traps. Despite a small number of parameters, the model is capable of accurately capturing the measurement results over a wide range of device operation from weak to strong inversion. Explicit expressions of device parameters also allow for the extraction of the oxide- and interface-trapped charge density.

Fig: Energy band diagrams illustrating interface charge trapping in bulk n- (a) and pMOSFETs (b) in inversion. The quasi-Fermi level of the minority carriers, 𝐸𝐹𝑛 or 𝐸𝐹𝑝, is split from that of the majority carriers 𝐸𝐹 by the channel voltage 𝑉𝑐ℎ

Acknowledgements: The authors would like to thank the EP-ESE group at CERN, especially Dr. Federico Faccio, for the continuous support in radiation measurements and the interesting discussions about data analysis. This work was supported in part by the Swiss National Science Foundation (SNSF) through the GigaradMOST project under grant number 200021_160185 and in part by the Istituto Nazionale di Fisica Nucleare (INFN) through the ScalTech28 Project.

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January 07, 2021 at 11:39AM
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Junior Scientist (PhD candidate) Positions

♦ Ferroelectric Vertical Nanowire Field Effect Transistors Development
at NaMLab, Dresden (Germany) and at University of Bordeaux (France)
Contact:
Dr.-Ing. Jens Trommer, NaMLab gGmbH 
Dr. Marina Deng, University of Bordeaux 

♦ Millimetre-wave (mmWave) Device; Silicon Waveguide Technologies for future > 100 GHz Applications
at School of Engineering, UC Louvain 
Contact:
Prof. Dimitri Lederer, UC Louvain 

♦ Modeling of Single Photon Avalanche Photodiode Temporal Response
at Institut d'Optique Graduate School, Univ. Saint-Etienne and STM (Crolles)
Contact:
Prof. Raphael Clerc, Univ. Saint-Etienne
Dr. Ing. Denis Rideau, STM

Jan 6, 2021

Virtual Si Museum /2101/ Electron Devices Time Line

my own view on the electron devices time line. The electron devices scaling: from a single vacuum tube, a BJT, TTL digital ICs to 68719476736 devices in a NAND flash memory card. If you have something else to add, just let me know:

REF:
  1. Vacuum Tube GE 9-22 188-5
  2. 2N2905A BJT - PNP, -60 V, -600 mA, 600 mW, TO-39
  3. TTL 74F00 IC - 5V, quad 2-input NAND gate; series F (=fast) introduced in 1978
  4. 64Gb NAND flash memory card

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January 06, 2021 at 02:13PM
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