Emerging Technologies Initiative (ETI)

Emerging Technologies Initiative (ETI)

What are classified as emerging technologies?

Emerging technologies have the potential to disrupt many existing industries and significantly impact employment, security, social equity, and global relations. However, it is important to note that disruptive innovations are not just a result of new technologies.  Incremental innovations in products and processes or aggregation of clustering of technologies can also combine to result in disruptive innovation – as seen recently in the case of several FinTech and AgriTech applications. 

For the purpose of this initiative, an indicative list of technologies are given below for the reference (including but not limited to):

What are the expected outcomes of ETI?

• Develop a critical mass of individuals/groups who are interested in thinking at the intersection of ‘Science & Technology’ and ‘International Engagement’
• Identify and prioritize the technologies of relevance and importance (present as well as future)
• Map technology and innovation hubs in India to anticipate the policy implications of the latest developments in emerging technologies
• Build a comprehensive Technology Intelligence Database (TID) for identified technologies. 
• Provide evidence-informed policy choices and program roadmaps for technology indigenization (reducing tech dependency and increasing domestic tech intensity)   
• Develop and strengthen the tech-knowledge capacity of central and state ministries, departments,  industries, accelerators and startups with the help of TID.
• Operationalize the technology indigenization roadmaps with identified stakeholders onboard
• Act as a synapsis amongst different stakeholders by facilitating the exchange of knowledge, expertise, and services to develop the emerging technology ecosystem.

[read more...]

Partners:

• The Office of the Principal Scientific Adviser to the Government of India (Office of PSA)
• New Emerging & Strategic Technologies Division in the Ministry of External Affairs (NEST, MEA #NESTMEA)
• Science Policy Forum (SPF)

[paper] Scaled GaN-HEMT Large-Signal Model Based on EM Simulation

Scaled GaN-HEMT Large-Signal Model Based on EM Simulation

Wooseok Lee¹, Hyunuk Kang¹, Seokgyu Choi², Sangmin Lee², Hosang Kwon³, Keum cheol Hwang¹, Kang-Yoon Lee¹ and Youngoo Yang¹

Electronics 2020, 9(4), 632

DOI: 10.3390/electronics9040632

¹Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon 16419, Korea
²Wavice Inc., Hwaseong-si 18449, Korea
³Agency for Defense Development, Daejeon 34186, Korea

Abstract This paper presents a scaled GaN-HEMT large-signal model based on EM simulation. A large-signal model of the 10-finger GaN-HEMT consists of a large-signal model of the two-finger GaN-HEMT and an equivalent circuit of the interconnection circuit. The equivalent circuit of the interconnection circuit was extracted according to the EM simulation results. The large-signal model for the two-finger device is based on the conventional Angelov channel current model. The large-signal model for the 10-finger device was verified through load-pull measurement. The 10-finger GaN-HEMT produced an output power of about 20 W for both simulation and load-pull measurements. 

Fig: Two-finger GaN-HEMT: a) layout; b) equivalent SPICE subcircuit

Acknowledgement: The research reported in this work has been supported by ADD (Agency of Defense Development) of Korea under an R&D program (UC170025FD).

[webinar] GaN HEMT Devices Characterization Using ASM-HEMT Model

ASM-HEMTモデルを使ったGaN HEMTデバイスの特性評価とモデリング

お知らせ: キーサイト・テクノロジーのウェブセミナー「ASM-HEMTモデルを使ったGaN HEMTデバイスの特性評価とモデリング 」

ライブウェブセミナーの日付: 2020年10月14日

ライブウェブセミナーの時刻: 10:45 JST

The Evolution of SPICE Continues With PSPICE for TI https://t.co/gBbrLEU2NJ #semi https://t.co/moYCCqfd1Y

The Evolution of SPICE Continues With PSPICE for TIhttps://t.co/gBbrLEU2NJ#semi pic.twitter.com/moYCCqfd1Y

— Wladek Grabinski (@wladek60) October 15, 2020

---

from Twitter https://twitter.com/wladek60

October 15, 2020 at 12:16PM
via IFTTT

[C4P] ICMTS: April 12 - 15, 2021

34th International Conference on Microelectronic Test Structures

ICMTS: April 12 - 15, 2021

Crowne Plaza Cleveland at Playhouse Square, Cleveland, OH, USA

Looking for the best opportunity to present and discuss your ideas and results about test structures, measurements and characterization? This is your chance! Join the 34th ICMTS conference. A Tutorial Short Course will precede the main conference. Several of the best measurement, equipment design, and manufacturing experts, will participate in the equipment exhibition and presentations. The conference will bring together designers and users of test structures to discuss recent developments and future directions, in a one-track program, with convivial breaks allowing attendees to discuss and exchange viewpoints and challenges. A Best Paper award will be presented by the Technical Program Committee. The IEEE Electron Devices Society is the co-sponsor, and all presented papers will be submitted for possible inclusion on IEEE Xplore®. Original papers are solicited presenting new developments in topics relevant to ICMTS, including but not limited to, test structures, measurements, and results, in the following areas:

• Design
• Methodologies, verification
• Within-die circuits for process characterization/monitoring
• Design enablement – Characterization and validation of digital and analog libraries
• Measurement techniques
• DC, AC and RF measurements: setup, test and analysis
• Reliability test - including thermal stability, failure analysis etc.
• Statistical analysis, variability, throughput increase, smart test strategies
• Use of machine learning and AI in analysis of data sets - parameter extraction etc.
• Wafer probing, within-die measurements, in-line metrology
• Throughput, testing strategies, yield enhancement and process control tests
• Applications
• Emerging memory technologies (single cell, arrays, and application in neural networks)
• Emerging transistor technologies for digital/analog/power applications
• Photonic devices - silicon integration, new displays (OLED, µ-displays)
• Flexible electronics and sensors (organic and inorganic materials)
• M(N)EMS, actuators, sensors, PV cells and other emerging devices

The author’s abstract submission consists of up to four pages in PDF format (font-embedded). The first page should include a title, a 50-word summary, author name(s), full address, contact number, and e-mail of the lead author, and any preference for oral or poster session presentation. The body of the abstract should consist of one page of text (800 to 1000 words) and up to two pages of major figures and tables. The selection process will be based on the technical merit and will be highly weighted in favor of abstracts with high test structure content (including illustration) along with measurements and data analysis.

The abstract submission deadline is November 6, 2020.

Abstracts can be submitted via the ICMTS website http://www.icmts.net using the “Submit Abstract” link on the front page. Notice of paper acceptance will be sent to the selected authors by mid-January, 2020, with instructions for the expanded manuscript preparation for the conference proceedings. The deadline for submission of the final paper will be March 17, 2021. 

Please join the ICMTS group at www.linkedin.com/groups/3804498, if you have in interest all things test structure related.

Details of the venue, hotel, registration, etc. will be posted at the ICMTS official web site. ICMTS is currently planned to be in person with the possibility of going virtual if necessary.

For further technical information, please contact the technical program chair:Chadwin Young, University of Texas at Dallas.

General Chair:

Brad Smith NXP Semiconductors

Technical Program Chair:

Chadwin Young University of Texas, Dallas

Tutorial Chair:

Matthew Rerecich Samsung Austin Semiconductor, LLC

Equipment Exhibition Chair:

Garrett Tranquillo Celadon Systems, Inc.

Local Arrangements:

Brad Smith NXP Semiconductors

ICMTS Steering Committee:

Asian Representative:

Satoshi Habu Keysight Technologies, Japan

European Representative:

Hans Tuinout NXP Semiconductors

USA Representative:

Bill Verzi Semiconductor Test Advisor