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[paper] TFETs for sensitive THz detection

I. Gayduchenko^1,2, S.G. Xu^3,4, G. Alymov¹, M. Moskotin^2,1, I. Tretyakov⁵, T. Taniguchi⁶, K.Watanabe⁷, G. Goltsman⁸, A.K. Geim^3,4, G. Fedorov^1,2, D. Svintsov¹, and D.A. Bandurin^3,1

Tunnel field-effect transistors for sensitive terahertz detection

arXiv:2010.03040 (2020)

¹Moscow Institute of Physics and Technology (National Research University), Dolgoprudny 141700, Russia
²Physics Department, Moscow Pedagogical State University, Moscow, 119435, Russia
³School of Physics, University of Manchester, Oxford Road, Manchester M13 9PL, United Kingdom
⁴National Graphene Institute, University of Manchester, Manchester M13 9PL, United Kingdom
⁵Astro Space Center, Lebedev Physical Institute of the Russian Academy of Sciences, Moscow 117997, Russia
⁶International Center for Materials Nanoarchitectonics, National Institute of Material Science, Tsukuba 305-0044, Japan
⁷Research Center for Functional Materials, National Institute of Material Science, Tsukuba 305-0044, Japan
⁸National Research University Higher School of Economics, Moscow, 101000, Russia

Abstract: The rectification of high-frequency electromagnetic waves to direct currents is a crucial process for energy harvesting, beyond 5G wireless communications, ultra-fast science, and observational astronomy. As the radiation frequency is raised to the sub-terahertz (THz) domain, efficient ac-to-dc conversion by conventional electronics becomes increasingly challenging and requires alternative rectification protocols. Here we address this challenge by tunnel field-effect transistors made of dual-gated bilayer graphene (BLG). Taking advantage of BLG’s electrically tunable band structure, we create a lateral tunnel junction and couple it to a broadband antenna exposed to THz radiation. The incoming radiation is then down-converted by strongly non-linear interband tunneling mechanisms, resulting in exceptionally high-responsivity (exceeding 3kV/W) and low-noise (0.2pW/Hz−−−√)  detection at cryogenic temperatures. We demonstrate how the switching from intraband Ohmic to interband tunneling regime within a single detector can raise its responsivity by one order of magnitude, in agreement with the developed theory. Our work demonstrates an unexpected application of interband tunnel transistors for high-frequency detection and reveals bilayer graphene as one of the most promising platforms therefor.

Fig: Overview of THz detectors. NEP for THz detectors of various types plotted against the temperature at which they operate. Vertical error bars represent the spread of the detectors’ performance over the frequency range 0.1−2 THz. Horizontal error bars show the temperature range at which the detectors operate.  

Acknowledgements: This work was supported by the Russian Foundation for Basic Research within Grants No. 18-37-20058 and No. 18-29-20116. Experimental work of IG (photoresponse measurements) was supported by the Russian Foundation for Basic Research (grant 19-32-80028). We acknowledge support of the Russian Science Foundation grant No. 19-72-10156 (NEP analyses) and grant No.17-72-30036 (transport measurements). The work of GA and DS (theory of THz detection) was supported by grant # 16-19-10557 of the Russian Scientific Foundation. K.W. and T.T. acknowledge support from the Elemental Strategy Initiative conducted by the MEXT, Japan, Grant Number JPMXP0112101001, JSPS KAKENHI Grant Number JP20H00354 and the CREST(JPMJCR15F3), JST. The authors thank A. Lisauskas, W. Knap, A. I. Berdyugin and M.S. Shur for helpful discussions.

[paper] Compact Modeling of GaN HEMTs

Y. Chen et al., "Compact Modeling of THZ Photomixer Made from GaN HEMT," 2020 IEEE International Conference on Advances in Electrical Engineering and Computer Applications (AEECA), Dalian, China, 2020, pp. 484-489, doi: 10.1109/AEECA49918.2020.9213681.

Y. Chen et al., "A Surface Potential Based Compact Model for GaN HEMT I-V and CV Simulation," 2020 IEEE International Conference on Advances in Electrical Engineering and Computer Applications (AEECA), Dalian, China, 2020, pp. 490-495, doi: 10.1109/AEECA49918.2020.9213674.

A. Zhang et al., "Compact Modeling of Capacitance Components for GaN HEMTs," 2020 IEEE International Conference on Advances in Electrical Engineering and Computer Applications (AEECA), Dalian, China, 2020, pp. 505-511, doi: 10.1109/AEECA49918.2020.9213571.

FIG: Simplified GaN HEMT Structure

[chapter] Low-Voltage Analog IC Design

Deepika Gupta¹

Low-Voltage Analog Integrated Circuit Design

Nanoscale VLSI. Book series (ESIEE) (2020) pp 3-22

DOI: 10.1007/978-981-15-7937-0_1

¹Department of Electronics and Communication Engineering, IIIT Naya Raipur, India

Abstract: In this chapter, we review the challenges and effective design techniques for ultra-low-power analog integrated circuits. With the miniaturization, having low-power low-voltage mixed signal IC is essential to maintain the electric field in the device. This constraint presents bottleneck for the researchers to design robust analog circuits. Specifically, the low value of supply voltage with small technology influences many specifications of analog IC, e.g., power supply rejection, dynamic range and immunity to noise, etc. In addition, it also affects the ability of the MOS transistor to be operated in the strong inversion region. Note that with the technology reduction, power supply VDD is reducing but the threshold voltage VT is not decreasing proportionally to maintain low leakage current. However, this process reduces the overdrive voltage and limits the staking of transistors. In this case, the transistor can be made to work in weak inversion to work and reduce the power consumption. Further, reduction in VDD to achieve low-power consumption causes many other circuit-related issues such as PVT variations, degradation of dynamic range, mismatching in circuits element and differential paths. There have been many design methods developed for the ultra-low-power analog ICs. In this chapter, we will discuss some of the design techniques to reduce the power consumption in analog ICs. In addition, we will also discuss the basic building blocks of analog circuits with discussed design techniques. The charge-based EKV model can be a very suitable example of a MOS simulation model to be used in all inversion regions of transistor operations [Enz 2017]. In EKV model, the smallest number of core parameters is needed for the accurate behavioral modeling of transistor. Particularly, charge-based EKV model is beneficial for the analysis of analog circuits because it allows the analysis with simple calculations over different inversion regions. Hence, developing new device simulation models specific for analog circuit design is crucial.

Fig: Vth and Vdd scaling trend vs. Leff  [Zhao 2006]

References:

[Enz 2018] Enz C, Chicco F, Pezzotta A (2017) Nanoscale MOSFET modeling-part 1: the simplified EKV model for the design of low-power analog circuits. IEEE Solid-State Circuits Magazine 9(3):26–35

[Zhao 2006] Zhao W, Cao Y (2006) New generation of predictive technology model for sub-45 nm early design exploration. IEEE Trans Electron Devices 53(11):2816–2823

[paper] TCAD-Machine Learning Framework

Hiu Yung Wong¹ (Senior Member, IEEE), Ming Xiao², Boyan Wang², Yan Ka Chiu¹, Xiaodong Yan³, Jiahui Ma³, Kohei Sasaki⁴, Han Wang³ (Senior Member, IEEE)

and Yuhao Zhang² (Member, IEEE)

TCAD-Machine Learning Framework for Device Variation and Operating Temperature Analysis with Experimental Demonstration

IEEE J-EDS, vol. 8, pp. 992-1000, 2020

doi: 10.1109/JEDS.2020.3024669.

¹Department of Electrical Engineering, San Jose State University, San Jose, CA 95112, USA
²Virginia Polytechnic Institute, State University, Blacksburg, VA 24060, USA
³Ming Hsieh Department of Electrical Engineering, University of Southern California, Los Angeles, CA 90089, USA
⁴Development Department, Novel Crystal Technology Inc., Sayama 3501328, Japan

Abstract: This work, for the first time, experimentally demonstrates a TCAD-Machine Learning (TCADML) framework to assist the analysis of device-to-device variation and operating (ambient) temperature without the need of physical quantities extraction. The ML algorithm used in this work is the Principal Component Analysis (PCA) followed by third order polynomial regression. After calibrated to limited ‘expensive’ experimental data, ‘low cost’ TCAD simulation is used to generate a large amount of device data to train the ML model. The ML was then used to identify the root cause of device variation and operating temperature from any given experimental current-voltage (I-V) characteristics. We applied this framework to study the ultra-wide-bandgap gallium oxide (Ga2O3) Schottky barrier diode (SBD), an emerging device technology that holds great promise for temperature sensing, RF, and power applications in harsh environments. After calibration, over 150,000 electrothermal TCAD simulations are performed with random variation of physical parameters (anode effective work function, drift layer doping, and drift layer thickness) and operating temperature. An ML model is trained using these TCAD data and we found 1,000-10,000 TCAD data can train an accurate machine. We show that without physical quantities extraction, performing PCA is essential for the TCAD trained ML model to be applicable to analyze experimental characteristics. The physical parameters and temperatures predicted by the ML model show good agreement with experimental analysis. Our TCAD-ML framework shows great promise to accelerate the development of new device technologies with a significantly more efficient process of material and device experimentation.

FIG: Flow chart diagram of the proposed TCAD-Machine Learning framework. All components are demonstrated in this article except the MLDatabase which stores previously trained ML algorithms.

Acknowledgment: The authors thank Dr. Pooya Jannaty of Cruise and Dr. Philip Leong of the University of Sydney for the discussion of ML algorithms. The experimental work is in part supported by the Southeastern Center for Electrical Engineering Education program and the High Density Integration industry mini-consortium of the Center for Power Electronics Systems at Virginia Tech.