Jul 29, 2020

Jerzy Ruzyllo - Guide to Semiconductor Engineering

Guide to Semiconductor Engineering
Jerzy Ruzyllo1 (Pennsylvania State University, USA)
World Scientific Book Series. March 2020
This Guide to Semiconductor Engineering is concerned with semiconductor materials, devices and process technologies which in combination are the driving force behind the unprecedented growth of our technical civilization over the last half a century. This book was conceived and written keeping in mind those who need to learn about semiconductor engineering, who are professionally associated with select aspects of this technical domain and want to see it in a broader context, or are simply interested in semiconductors. In its coverage of semiconductor engineering this Guide departs from textbook-style, monothematic in-depth coverage of topics such as the physics of semiconductors and semiconductor devices, the manufacturing of semiconductor devices and circuits, and the characterization of semiconductor materials. Instead, it covers the entire field of semiconductor engineering in one concise volume with synergistic interactions between various areas clearly identified. It is a holistic approach to the coverage of semiconductor engineering which makes this guide unique among books covering semiconductor related issues available on the market today. 
[Table of Contents]
1Jerzy Ruzyllo is a Distinguished Professor Emeritus in the School of Electrical Engineering and Computer Science at the Pennsylvania State University. He joined Penn State in 1984 after completing his education, obtaining a PhD degree in 1977, and serving on the faculty of the Warsaw University of Technology in Poland. Throughout his career, Dr Ruzyllo was actively involved in research and teaching in the area of semiconductor science and engineering. Dr Ruzyllo is a Life Fellow of IEEE and Fellow of the Electrochemical Society.

Jul 27, 2020

Jan #Czochralski And The #Silicon #Revolution https://t.co/LMX4tiAuIQ #semi https://t.co/zKPirLDPji



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July 27, 2020 at 11:46AM
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[paper] Compact Source-Gated Sensor

Eva Bestelink, Student Member, IEEE, Kham M. Niang, Georgios Bairaktaris, Luca Maiolo, Francesco Maita, Kalil Ali, Andrew J. Flewitt, S. Ravi P. Silva
and Radu A. Sporea, Senior Member, IEEE
Compact Source-Gated Transistor Analog Circuits for Ubiquitous Sensors
In IEEE Sensors. Jul 18, 2020

Abstract: Silicon-based digital electronics have evolved over decades through an aggressive scaling process following Moore’s law with increasingly complex device structures. Simultaneously, large-area electronics have continued to rely on the same field-effect transistor structure with minimal evolution. This limitation has resulted in less than ideal circuit designs, with increased complexity to account for shortcomings in material properties and process control. At present, this situation is holding back the development of novel systems required for printed and flexible electronic applications beyond the Internet of Things. In this work we demonstrate the opportunity offered by the source-gated transistor’s unique properties for low-cost, highly functional large-area applications in two extremely compact circuit blocks. Polysilicon common-source amplifiers show 49 dB gain, the highest reported for a twotransistor unipolar circuit. Current mirrors fabricated in polysilicon and InGaZnO have, in addition to excellent current copying performance, the ability to control the temperature dependence (degrees of positive, neutral or negative) of output current solely by choice of relative transistor geometry, giving further flexibility to the design engineer. Application examples are proposed, including local amplification of sensor output for improved signal integrity, as well as temperature-regulated delay stages and timing circuits for homeostatic operation in future wearables. Numerous applications will benefit from these highly competitive compact circuit designs with robust performance, improved energy efficiency and tolerance to geometrical variations: sensor front-ends, temperature sensors, pixel drivers, bias analog blocks and high-gain amplifiers.

FIG: a) Photomicrograph of a typical polysilicon SGT fabricated; b) Driver M1 output characteristics (black curves, VGmax = -15 V, step 0.5 V) and superimposed M2 load line (orange, VG = 0 V). VSAT1 occurs as a result from pinch-off at the source and VSAT2 represents channel pinch-off of the parasitic FET. 

Acknowledgment: R.A.S. acknowledges the Royal Academy of Engineering of Great Britain for the support through the Research Fellowship (Grant No. 10216/110), the Royal Society of Great Britain through project ARES IES\R3\170059 and EPSRC for grants EP/R028559/1 and EP/R025304/1. K.M.N. and A.J.F. acknowledge the support of the Engineering and Physical Sciences Research Council (EPSRC) through project EP/M013650/1. R.A.S. thanks Prof John Shannon for technical discussions, Dr Nigel Young and Dr Michael Trainor for assistance with polysilicon device design and fabrication.

#Intel Plunges as It Weighs #Exit From Manufacturing Chips https://t.co/Yxg9KUq5iT #semi https://t.co/fJDOLaFTKD



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July 27, 2020 at 09:47AM
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[FOSSi] OpenLANE: Open Source 130nm PDK

Join Mohamed Shalan for the 2nd talk in the Free and Open Source Silicon (FOSSi) Foundation Dial-Up series is on Tuesday 28th July, he will talk about OpenLANE on the first-in-the-industry Open Source Manufacturable SkyWater 130nm PDK

Mohamed Shalan - OpenROAD on SkyWater 130nm

Unlike the wider software world, Electronic Design Automation (EDA) open-source landscape has been fragmented for a long time, requiring significant effort and knowledge in a variety of disciplines to assemble a working ASIC flow. This has changed with projects such as Qflow and OpenROAD that aim at developing open-source toolchain for digital layout generation from RTL. OpenLane is an automated RTL to GDSII flow based on available opensource EDA tools configured/tuned for the SkyWater 130nm PDK. OpenLane main objective is to generate a clean layout from RTL designs in less than 24-hours with zero human interventions. OpenLane has been used, successfully, to tape-out a family of test chips (striVe).

Join live on YouTube on Tuesday July 28 at 16:00GMT https://lnkd.in/gCyMuPp