Jul 14, 2020

[RG] research paper reached 500 citations


FOSS EKV2.6 Verilog-A Compact MOSFET Model
Wladek Grabinski1, Marcelo Pavanello2, Michelly de Souza2, Daniel Tomaszewski3, Jola Malesinska3, Grzegorz Głuszko3, Matthias Bucher4, Nikolaos Makris4, Aristeidis Nikolaou4, Ahmed Abo-Elhadid5, Marek Mierzwinski6, Laurent Lemaitre7, Mike Brinson8, Christophe Lallement9, Jean-Michel Sallese10, Sadayuki Yoshitomi11, Paul Malisse12, Henri Oguey13, Stefan Cserveny13, Christian Enz10, François Krummenacher10 and Eric Vittoz10 
in 49th European Solid-State Device Research Conference 
(ESSDERC; pp. 190-193)

DOI: 10.1109/essderc.2019.8901822 

FOSS EKV2.6 Verilog-A at GitHub https://github.com/ekv26/model

1 MOS-AK Association (EU), 
2 Centro Universitario FEI, Sao Bernardo do Campo (BR), 
3 Institute of Electron Technology, Warsaw (PL), 
4 Technical University of Crete, Chania (GR), 
5 Mentor Graphics (USA), 
6 Keysight Technologies (USA), 
7 Lemaitre EDA Consulting, 
8 London Metropolitan University (UK), 
9 ICube, Strasbourg University (F), 
10 EPFL Lausanne, 
11 Toshiba (J), 
12 Europractice/IMEC (B), 
13 CSEM S.A., Neuchatel (CH)

[paper] Carbon Nanotube Detectors and Spectrometers for the Terahertz Range

Junsung Park1, Xueqing Liu1, Trond Ytterdal2
and Michael Shur1,3 
Carbon Nanotube Detectors and Spectrometers for the Terahertz Range 
Crystals 2020, 10, 601
DOI:10.3390/cryst10070601

1Department of Electrical, Computer, and Systems Engineering, RPI  Troy, NY 12180, USA
2Department of Electronic Systems, NUST, O.S. Bragstads plass 2a, 7034 Trondheim, N
4Electronics of the Future, Inc., Vienna, VA 22181, USA

Abstract: We present the compact unified charge control model (UCCM) for carbon nanotube field-effect  transistors  (CNTFETs)  to  enable the accurate  simulation  of  the  DC  characteristics  and plasmonic terahertz (THz) response  in the  CNTFETs. Accounting for  the ambipolar  nature of the carrier transport (n-type and p-type conductivity at positive and negative gate biases, respectively), we use n-type and p-type CNTFET non-linear equivalent circuits connected in parallel, representing the ambipolar  conduction in the  CNTFETs.  This allows us to present a realistic non-linear  model that is valid across the  entire voltage  range  and is therefore suitable  for  the  CNTFET design. The important  feature  of  the  model  is that  explicit equations for gate  bias,  current,  mobility,  and capacitance with smoothing parameters accurately describe the device operation near the transition from above- to below-threshold regimes, with scalability in device geometry. The DC performance in  the proposed  compact CNTFET  model  is  validated  by  the  comparison between  the  SPICE simulation and the experimental DC characteristics. The simulated THz response resulted from the validated CNTFET model is found to be in good agreement with the analytically calculated response and  also  reveals  the  bias  and  power  dependent  sub-THz  response  and  relatively  wide  dynamic range   for   detection   that   could   be   suitable   for   THz   detectors.   The   operation   of   CNTFET spectrometers  in the THz  frequency  range  is  further  demonstrated  using  the  present  model.  The simulation exhibits that the CNT-based spectrometers can cover a broad THz frequency band from 0.1 to 3.08 THz. The model that has been incorporated into the circuit simulators enables the accurate assessment  of  DC  performance  and  THz  operation.  Therefore,  it  can  be  used  for the design  and performance estimation of the CNTFETs and their integrated circuits operating in the THz regime.  

Fig: Schematic illustration of the simulation circuit for the CNTFET THz detection
with the open boundary condition at the drain.

Funding: This  work  at  RPI  was  supported  by  the  U.S.  Army  Research  Laboratory  under  the  Cooperative Research Agreement (Project Monitor Dr. Meredith Reed) and by the US ONR (Project Monitor Dr. Paul Maki). 

[paper] An ambipolar homojunction with options

Yanqing Wu
An ambipolar homojunction with options
Nat Electron (2020)
Published 13 July 2020
DOI: 10.1038/s41928-020-0447-3

Circuits capable of reconfigurable logic and neuromorphic functions can be created by exploiting the electronic tunability of two-dimensional tungsten diselenide homojunctions.


Fig: Reconfigurable ambipolar WSe2 homojunction devices and circuits. a, Schematic of a WSe2 homojunction device that consists of two polarity-control embedded gates. b, Using two of these devices, a reconfigurable circuit cell can be created (top) that has a multifunctionality controlled through combinations of gate voltage and drain voltage. The circuit has three input terminals, two of which connect to the polarity gate of one of the devices and the drain of the other device. Using different combinations of the three inputs, seven different Boolean functions can be achieved, including pass, inverter, two-input OR, AND, and borrow-out, as listed in the truth table (bottom). Vds, drain–source voltage; VgA and VgB, gate bias for partial gates A and B, respectively; Vin1, Vin2 and Vin3, input voltages for input terminals 1, 2 and 3, respectively; M1 and M2, homojunction devices 1 and 2, respectively; Vout, output voltage; A, B and C represent logic states of either ‘0’ or ‘1’.

Jul 8, 2020

[paper] compact nanowire JAM-MOSFET model

Kamalaksha Baral, Prince Kr Singh, Sanjay Kumar, Manas Ranjan Tripathy,
Ashish Kr Singh, Sweta Chander and S JitA
2-D compact DC model for engineered nanowire JAM-MOSFETs 
valid for all operating regimes
Semiconductor Science and Technology, Vol. 35, No. 8

Abstract: This manuscript reports a 2-D compact analytical model for DC characteristics under all possible regimes of operations of a cylindrical gate (CG) nanowire junctionless accumulation mode (JAM) MOSFET including the effects of various device engineering techniques. Superposition technique with appropriate boundary conditions has been used to solve 2-D Poisson’s equation considering both free/accumulation and depletion charges. The minimum potential concept has been used to conceive the threshold voltage formulation considering the effects of structural and electrical quantum confinements. An optimized device model has been formulated incorporating various device engineering. The potential model could also be used for potential modeling of doped inversion mode MOSFETs. Complete drain current including gate induced drain leakage (GIDL) has been derived from the potential model. Drain current has been derived individually for different regions. Further the effects of temperature and trapped interface charges have been included in the model. A 3-D commercial TCAD has been used to validate the model results of our proposed device. 
Fig: A 2-D cross-sectional view of cylindrical gate nanowire
junctionless accumulation mode MOSFET 



Jul 7, 2020

[mos-ak] [Final Program] MOS-AK Workshop at ESSDERC/ESSCIRC,Grenoble, Sept.14, 2020

Arbeitskreis Modellierung von Systemen und Parameterextraktion
Modeling of Systems and Parameter Extraction Working Group
MOS-AK Workshop as ESSDERC/ESSCIRC Virtual Educational Event
Grenoble, September 14, 2020

Together with local ESSDERC/ESSCIRC Organization Team as well as International MOS-AK Board of R&D Advisers and all the Extended MOS-AK TPC Committee, we have the pleasure to invite to consecutive, 18th MOS-AK Workshop as ESSDERC/ESSCIRC Virtual Educational Event

Scheduled, subsequent 18th MOS-AK Workshop organized as an integral part of the ESSDERC/ESSCIRC Confernces, aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and TCAD/EDA FOSS and commercial tool developers and vendors. 

MOS-AK Workshop Program
includes 8 webinars by the internationally recognized compact modeling experts: 
W_1 Qucs-S and QucsStudio for compact device modelling.
Mike Brinson
London Metropolitan University (UK)
W_2 Memory Modeling for Neuromorphic Computing
Mansun Chan
Hong Kong University of Science & Technology (HK)
W_3 Compact Modeling of Oxide and Organic Thin Film Transistors
Benjamin Iniguez
Universitat Rovira i Virgili, Tarragona (SP)
W_4 Latest developments of L-UTSOI: 
A compact model dedicated to low-power analog and digital applications in FDSOI technologies
Sébastien Martinie
CEA-Leti, Grenobel (F)
W_5 Overview of the ASM-HEMT Model
Yogesh Chauhan
IIT Kanpur (IN)
W_6 ngspice - current status and developments
Holger Vogt
Fraunhofer IMS, Duisburg (D)
W_7 LDMOS compact modeling and the PSPHV model
Kejun Xia
NXP (USA)
W_8 Nanowire Junctionless ISFETs
Ashkhen Yesayan
Institute of Radiophysics and Electronics National Academy of Sciences (AM)

The MOS-AK program is available online: <http://www.mos-ak.org/grenoble_2020/>

Venue:
Virtual Educational Event at ESSDERC/ESSCIRC  
 
(any related enquiries can be sent to registration@mos-ak.org)

W.Grabinski on the behalf of International MOS-AK Committee
WG07072020

--
You received this message because you are subscribed to the Google Groups "mos-ak" group.
To unsubscribe from this group and stop receiving emails from it, send an email to mos-ak+unsubscribe@googlegroups.com.
To view this discussion on the web visit https://groups.google.com/d/msgid/mos-ak/4265562c-ce4f-40f7-ac3f-278ebc2ede12o%40googlegroups.com.