Understand #MOSFET Switch Behavior Via An #LED Driver #Simulation https://t.co/sQ4KYaQpX2 #paper https://t.co/Z2x0VHLVTG

Understand #MOSFET Switch Behavior Via An #LED Driver #Simulation https://t.co/sQ4KYaQpX2#paper pic.twitter.com/Z2x0VHLVTG

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[paper] Compact Model for SIS Josephson Junctions

A Compact Model for Superconductor-Insulator-Superconductor (SIS) Josephson Junctions

Shamiul Alam, Mohammad Adnan Jahangir and Ahmedullah Aziz, Member, IEEE

Department of Electrical Engineering and Computer Science

University of Tennessee, Knoxville, TN, USA

in IEEE Electron Device Letters, 

DOI: 10.1109/LED.2020.3002448

Abstract: We present a Verilog-A based compact model for the superconductor-insulator-superconductor (SIS) Josephson junction. The model can generate both hysteretic and non-hysteretic current-voltage (I-V) response for the SIS junctions utilizing the Stewart-McCumber damping parameter. We calibrate our model with different SIS samples and demonstrate accurate matching between the simulated and experimental results. We implement temperature effect on the energy gap and the critical current of the superconductor to explore the dynamic trends in device characteristics. We calculate the junction inductance and stored energy as functions of junction current and temperature. We simulate the read/write operations of an SIS junction based cryogenic memory cell to illustrate the usability of our model.

Fig: (a) Device structure of an SIS Josephson junction
(b) the RCSJ model of a Josephson junction.

[paper] 3D Vertical JL GAA Si Nanowire Transistors

Chhandak Mukherjee¹, Guilhem Larrieu² and Cristell Maneuxsup¹

Compact Modeling of 3D Vertical Junctionless Gate-all-around Silicon Nanowire Transistors

EuroSOI-ULIS 2020, Sep 2020, Caen (F)

¹IMS Laboratory, University of Bordeaux, France

²LAAS-CNRS, Université de Toulouse, France 

HAL: hal.archives-ouvertes.fr/hal-02869216

Abstract: This paper presents a physics based, computationally efficient compact modeling approach for 3D vertical gate-all-around junctionless nanowire transistor (JLNT) arrays designed for future high performance computational logic circuit. The model features an explicit continuous analytical form adapted for a 14 nm channel JLNT technology and has been validated against extensive characterization results on a wide range of JLNT geometry, depicting good accuracy. Finally, preliminary logic circuit simulations have been performed for benchmarking performances of transistor logic circuits, such as inverters and ring oscillators, designed using the developed model.

Fig: The vertical JLNT: (a) SEM image of nanowire arrays, 

(b) single nanowire showing its (c) gate formation 

Acknowledgement: This work is supported by ANR under Grant ANR-18- CE24-0005-01

[webinar] Differentiated FDSOI for mmWave Solutions

WEBEX by IEEE EDS Santa Clara Valley/San Francisco Chapter

Differentiated Fully Depleted SOI (FDSOI) Technology 

for Highly Efficient and Integrated mmWave Wireless Connectivity Solution

Speaker: Dr. Anirban Bandyopadhyay,  Director, Strategic Marketing and Business Analytics, GLOBALFOUNDRIES, Inc., Santa Clara, CA

Friday, July 24, 2020 at 12PM – 1PM PDT

WEBEX ONLY: Click Here to Attend

Abstract: The emergence of enhanced mobile broadband (eMBB) connectivity based on mmWave 5G and the emerging prospect of broadband internet to using non-terrestrial mmwave backhaul using low earth orbit (LEO) satellite generated huge interest in the entire telecommunication ecosystem. While mmwave allows huge bandwidth of channels to enable enhanced broadband, it also poses a lot of technical challenges in terms of coverage, generating enough transmitted power efficiently particularly in the uplink, system cost & scaling and long term reliability of the hardware system particularly for infrastructure including Satellite born systems. Current talk will focus on how Silicon technologies based on differentiated fully depleted SOI (FDSOI) can address the above challenges by enabling a highly efficient and integrated radio without compromising on the mmWave performance and reliability. Talk will highlight the technology Figures of Merits (FOMs) for a mmwave phased array system and how a differentiated FDSOI technology platform compares with other silicon technologies in terms of devices and circuits.

Speaker Bio: Dr. Anirban Bandyopadhyay is the Director, Strategic Marketing and Business Analytics within the Mobility & Wireless Infrastructure Business Unit of GLOBALFOUNDRIES, USA. His work is currently focused on hardware architecture & technology evaluations for emerging RF and mmWave applications. Prior to joining GLOBALFOUNDRIES, he was with IBM Microelectronics, New York and with Intel, California where he worked on different areas like RF Design Enablement, Silicon Photonics, signal integrity in RF & Mixed signal SOC’s. Dr. Bandyopadhyay did his PhD in Electrical Engineering from Tata Institute of Fundamental Research, India and Post-Doctoral research at Nortel, Canada and at Oregon State University, USA. He represents Global Foundries in different industry consortia on RF/mmWave applications and is a Distinguished Lecturer of IEEE Electron Devices Society.

More information at the IEEE EDS Santa Clara Valley-San Francisco Chapter Home Page

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IEEE SSCS-EDS Distinguished Talks (Webinar) Systematic Design of Analog CMOS Circuits Dr. Paul Jespers, UCLouvain, Louvain-la-Neuve, Belgium July 09th, 13h30 (Brasilia Time, GMT-3) https://t.co/d3HL96l2xT https://t.co/FQOFMq4FJG #paper https://t.co/zelqSxMxGI

IEEE SSCS-EDS Distinguished Talks (Webinar)
Systematic Design of Analog CMOS Circuits
Dr. Paul Jespers, UCLouvain, Louvain-la-Neuve, Belgium
July 09th, 13h30 (Brasilia Time, GMT-3)https://t.co/d3HL96l2xT https://t.co/FQOFMq4FJG#paper pic.twitter.com/zelqSxMxGI

— Wladek Grabinski (@wladek60) June 29, 2020

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June 29, 2020 at 11:04AM
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