Jun 17, 2020

[paper] CV of Graphene–Silicon Heterojunction Photodiodes

Sarah Riazimehr,  Melkamu Belete,  Satender Kataria,  Olof Engström and Max Christian Lemme
Capacitance–Voltage (C –V) Characterization 
of Graphene–Silicon Heterojunction Photodiodes
Advanced Optical Materials 
First Published Open Access: 07 May 2020
DOI: 10.1002/adom.202000169

Abstract: Heterostructures of 2D and 3D materials form efficient devices for utilizing the properties of both classes of materials. Graphene/silicon (G/Si) Schottky diodes have been studied extensively with respect to their optoelectronic properties. Here, a method to analyze measured capacitance–voltage (C –V) data of G/Si Schottky diodes connected in parallel with G/silicon dioxide/Si (GIS) capacitors is introduced. The accurate extraction of the built‐in potential (Φbi) and the Schottky barrier height (SBH) from the measurement data independent of the Richardson constant is also demonstrated.
Figure 2
Fig.: a) Cross section of the test device showing both MIS and GIS regions. b) Small‐signal C –V characteristics of Dtest (line) compared to a theoretically calculated C –V curve (dashed ) at 10 kHz.

Acknowledgements: Financial support from the European Commission (Graphene Flagship, 785219, 881603) and the German Ministry of Education and Research, BMBF (GIMMIK, 03XP0210) is gratefully acknowledged.

[paper] Compact Model for Ferroelectric FET

Lu, Darsen, Sourav De, Mohammad Aftab Baig, Bo-Han Qiu, and Yao-Jen Lee
Computationally efficient compact model for ferroelectric field-effect transistors 
to simulate the online training of neural networks
Semiconductor Science and Technology (2020)
DOI: 10.1088/1361-6641/ab9bed

Abstract: In this paper, a compact drain current formulation that is simple and adequately computationally efficient for the simulation of neural network online training was developed for the ferroelectric memory transistor. Tri-gate ferroelectric field effect transistors (FETs) with Hf0.5Zr0.5O2 gate insulators were fabricated with a gate-first high-k metal gate CMOS process. Ferroelectric switching was confirmed with double sweep and pulse programming and erasure measurements. Novel characterization scheme for drain current was proposed with minimal alteration of ferroelectric state in subthreshold for accurate threshold voltage measurements. The resultant threshold voltage exhibited highly linear and symmetric across multilevel states. The proposed compact formulation accurately captured the FET gate-bias dependence by considering the effects of series resistance, Coulomb scattering, and vertical field dependent mobility degradation.
Fig.: Transmission electron micrograph of the fabricated tri-gate Fe
finFET device across the fin, with approximately 60 nm fin width, 30 nm fin
height, and 10 nm HZO Fe layer.

Acknowledgements: This work was jointly supported by the Ministry of Science and Technology (Taiwan) grant MOST–108–2634–F–006–08 and is part of research work by MOST’s AI Biomedical Research Center. We are grateful to the Taiwan Semiconductor Research Institute for nanofabrication facilities and services and to Dr. Wen-Jay Lee and Nan-Yow Chen of the National Center for High-Performance Computing for helpful suggestions on AI computation. This manuscript was edited by Wallace Academic Editing.

#Samsung #MOSIS Collaboration https://t.co/IOrXK5W1Y8 #paper https://t.co/VXZqf03bmY


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