#Korean researchers 3D print highly-sensitive, #wearable #biosensors https://t.co/ZnXxlGvSfS #paper https://t.co/7t2rVVC07n

#Korean researchers 3D print highly-sensitive, #wearable #biosensors https://t.co/ZnXxlGvSfS#paper pic.twitter.com/7t2rVVC07n

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#EU and #Japan step up cooperation in #science, #technology and innovation https://t.co/710WckAuB6 #Paper https://t.co/XdoU4mjQ3D

#EU and #Japan step up cooperation in #science, #technology and innovation https://t.co/710WckAuB6#Paper pic.twitter.com/XdoU4mjQ3D

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[paper] InAs-OI-Si MOSFET Compact Model

S. K. Maity, A. Haque and S. Pandit

Charge-Based Compact Drain Current Modeling of InAs-OI-Si MOSFET 

Including Subband Energies and Band Nonparabolicity

in IEEE TED, vol. 67, no. 6, pp. 2282-2289, June 2020

doi: 10.1109/TED.2020.2984578

Abstract: In this article, we report a physics-based compact model of drain current for InAs-on-insulator MOSFETs. The quantum confinement effect has been incorporated in the proposed model by solving the 1-D Schrödinger–Poisson equations without using any empirical model parameter. The model accurately captures the variation of surface potential, charge density in the inversion layer, and subband energy levels with gate bias inside the quantum well. The conduction-band nonparabolicity effect on modification in eigen energy, effective mass, and density of states is derived and incorporated into the proposed model. The velocity overshoot effect that originates from the quasi-ballistic nature of carrier transport is also considered in the model. The proposed drain current model has been implemented in Verilog-A to use in the SPICE environment. The model predicted results are in good agreement with the commercial device simulator results and experimental data. 

Fig: Energy band profile of InAs-OI-Si MOSFET in the direction perpendicular to the oxide interface at flat-band condition. E0 and E1 denote the first and the second subband energy levels, respectively, and ΔEc and Vox represent the conduction-band offset between buffer-channel and oxide-channel regions, respectively.

Acknowledgment: The author S. Pandit would like to thank the Department of Electronics and Information Technology, Government of India for utilizing the resources obtained under the SMDP-C2SD Project at the University of Calcutta.

URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9067014&isnumber=9098120

Open PhD Positions In The Eu-Funded Project "GREAT". Currently, there are still vacancies in Germany and France. You can find more information at: https://t.co/9I9kUDznV7 AMO GmbH | https://t.co/GS5EmAINfr #paper https://t.co/haPyrQLtG9

Open PhD Positions In The Eu-Funded Project "GREAT". Currently, there are still vacancies in Germany and France. You can find more information at: https://t.co/9I9kUDznV7
AMO GmbH | https://t.co/GS5EmAINfr#paper pic.twitter.com/haPyrQLtG9

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[paper] Organic Transistor Memory Based on Black Phosphorus Quantum Dots

P. Kumari, J. Ko, V. R. Rao, S. Mhaisalkar and W. L. Leong

Non-Volatile Organic Transistor Memory Based on Black Phosphorus Quantum Dots as Charge Trapping Layer,

in IEEE Electron Device Letters, vol. 41, no. 6, pp. 852-855, June 2020

doi: 10.1109/LED.2020.2991157

Abstract: High performance organic nano-floating gate transistor memory (NFGTM) has important prerequisites of low processing temperature, solution–processable layers and charge trapping medium with high storage capacity. We demonstrate organic NFGTM using black phosphorus quantum dots (BPQDs) as a charge trapping medium by simple spin-coating and low processing temperature ( 120 °C). The BPQDs with diameter of 12.6 ± 1.5 nm and large quantum confined bandgap of ~2.9 eV possess good charge trapping ability. The organic memory device exhibits excellent memory performance with a large memory window of 61.3 V, write-read-erase-read cycling endurance of 10 3 for more than 180 cycles and reliable retention over 10,000 sec. In addition, we successfully improved the memory retention to ON/OFF current ratio 10E4 over 10,000 sec by introducing PMMA as the tunneling layer.

 

FIG: a.) Schematic of bottom gate top contact NFGTM device; b.) Band diagram explaining memory mechanism under positive gate bias 

Acknowledgement: W.L. Leong would like to acknowledge funding support from her NTU start-up grant (M4081866), Ministry of Education (MOE) under AcRF Tier 1 grant (2016-T1-002- 097), Tier 2 grant (2018-T2-1-075), ASTAR AME IAF-ICP Grant (No.I1801E0030) and A*STAR AME Young Individual Research Grant (Project No. A1784c019).