[mos-ak] [Final Program] 12th International MOS-AK Workshop; Silicon Valley, Dec.11 2019

12th International MOS-AK Workshop

(co-located with the IEDM and Q4 CMC Meetings)

Silicon Valley, December 11, 2019

<http://www.mos-ak.org/silicon_valley_2019/>

Together with Silvaco team, the MOS-AK workshop host as well as International MOS-AK Board of R&D Advisers and all the Extended MOS-AK TPC Committee, we have the pleasure to invite to consecutive, 12th International MOS-AK Workshop is Silicon Valley.

Scheduled, subsequent 12th MOS-AK SPICE/Compact Modeling Workshop organized in the Silicon Valley, aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and TCAD/EDA tool developers and vendors. 

The MOS-AK workshop program is available online:

<http://www.mos-ak.org/silicon_valley_2019/>

Venue:

Silvaco 

2811 Mission College Blvd., 6th Floor 

Santa Clara, CA 95054

Online Registration is still open

(any related enquiries can be sent to register@mos-ak.org)

Postworkshop Publications:

Selected best MOS-AK technical presentation will be recommended for further publication
in a special Solid State Electronics issue on compact modeling 

W.Grabinski on the behalf of International MOS-AK Committee

WG02122019

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#Alibaba’s growing #opensource stature - Eyes on APAC https://t.co/W3qBN15Wsr https://t.co/DoR0OSzOMh

#Alibaba’s growing #opensource stature - Eyes on APAC https://t.co/W3qBN15Wsr pic.twitter.com/DoR0OSzOMh

— Wladek Grabinski (@wladek60) December 2, 2019

from Twitter https://twitter.com/wladek60

December 02, 2019 at 04:07PM
via IFTTT

[C4P] 50th ESSDERC / 46th ESSCIRC

Grenoble (F) Sept.14-18 2020

Call for Papers

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits. The level of integration for system-on-chip design is rapidly increasing. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers and system designers is necessary. While keeping separate Technical Program Committees, ESSDERC and ESSCIRC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both communities. Attendees registered for either conference are encouraged to attend any of the scheduled parallel sessions, regardless to which conference they belong.

TPC Tracks:

• Advanced Technology, Process and Materials
• Analog, Power and RF Devices
• Compact modeling and process/device simulation
  
• Joint TRACK: Memory devices and circuits towards non Von Neumann
• Joint TRACK: Emerging Computing Devices and Circuits
• Joint TRACK: Devices and circuits for Sensors, Optoelectronics and Display
  
• Analog Circuits
• Data Converters Circuits
• RF & mmW Circuits
• Frequency Generation Circuits
• Wireless & Wireline Circuits & Systems
• Digital Circuits & Systems
• Power Management Circuits

#paper A. Biswas, D. Ludwig and M. Cotorogea, "A New Computer-Aided Calibration Technique of Physics Based IGBT & Power-Diode Compact Models with Verilog-A Implementation," 2019 SISPAD, Udine, Italy, 2019, pp. 1-4. doi: 10.1109/SISPAD.2019.8870499 https://t.co/tM3k2ejZWs https://t.co/8bzoxK27ru

#paper
A. Biswas, D. Ludwig and M. Cotorogea, "A New Computer-Aided Calibration Technique of Physics Based IGBT & Power-Diode Compact Models with Verilog-A Implementation," 2019 SISPAD, Udine, Italy, 2019, pp. 1-4.
doi: 10.1109/SISPAD.2019.8870499 https://t.co/tM3k2ejZWs pic.twitter.com/8bzoxK27ru

— Wladek Grabinski (@wladek60) November 30, 2019

from Twitter https://twitter.com/wladek60

November 30, 2019 at 06:12PM
via IFTTT

PhD Positions at Institute for Microelectronics/TU Wien

PhD Positions
on Characterization, Modeling and Circuit Simulation in Microelectronics
Institute for Microelectronics/TU Wien

The Institute for Microelectronics is a world leading research institute focused on the reliability of circuit components (especially transistors). In addition to conventional Si transistors, the behavior of SiC devices designed for high-power applications is also at the center of interest. The broad field of research conducted at the Institute of Microelectronics ranges from characterization, physical modeling and ab-initio simulations to compact modeling and circuit simulation. For the characterization of transistors, the Institute for Microelectronics has a modern laboratory equipped with commercial and custom-built measurement instruments. To explain the experimental data, elaborate physical models are developed and constantly improved. The models are directly incorporated into state-of-the-art device simulators, i.e. MinimosNT and Comphy. To perform computationally expensive simulations a modern computer cluster is while for circuit simulations Cadence and Synopsis spice simulators are available.

The institute is currently looking for highly talented and motivated young researchers to join the team in one of the following areas:

• Physical modeling of silicon-carbide transistors
• Single-defect characterization of low-noise silicon transistors
• Development of custom-made measurement instruments
• Circuit simulations using advanced implementation of reliability models in Verilog-A for SPICE

For the positions knowledge in one or more of the following areas is advantageous to complement our team:

• C/C++ and Python
• Semiconductor device physics
• Circuit simulation
• Implementation of new compact/physical models
• Handling of device/circuit simulators
• Design of discrete analog circuits and hardware/software solutions
• Wafer probers and instruments for microelectronics
• Keithley instruments and scripting language LUA
• Measurement techniques in microelectronics (MSM, C(V), DLTS, charge pumping etc.)

As a teaching institution, knowledge transfer and close cooperation with students are very importance. The applicants should like to work together with students and supervise Master’s and Bachelor theses.

Starting Date: As soon as possible

Salary: Three-year positions (40hours/week) are in accordance with the salary regulations of the Austrian Science Fund. The gross annual salary is approximately EUR 40,300

Application Material: Please provide a detailed CV, your collective certificates, your Master’s thesis (weblink or PDF), and a single-page motivation letter (discussing relevant previous experience related to the desired skills and experiences) and summarize your motives for joining us.

Application: Please submit your application to jobs@iue.tuwien.ac.at.

Application Deadline: The positions will remain open until filled.