Jul 23, 2019

#IEEE Update of the International Roadmap for Devices and Systems (#IRDS) Sets Course for Computer and Electronics Industry Growth https://t.co/WwvxXl4Sq8 #paper https://t.co/ZOwLjWV0Sr


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July 23, 2019 at 05:31PM
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Looking for #Quality in #TCAD-Based Papers #IEEE #TED: “What is the definition of high quality?” In this editorial, at least partially, this question is addressed. https://t.co/c1G0YXgIdD #paper https://t.co/MbhLzUa4AZ


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July 23, 2019 at 02:11PM
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#IBM gives #cancer_killing drug AI project to the #OpenSource community | ZDNet https://t.co/GdgoUmx5UT https://t.co/lfC2v7MuFP


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July 23, 2019 at 11:34AM
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CODEOCEAN: Charge-Based Modeling of Long-Channel Symmetric Double-Gate Junction FETs

CODEOCEAN capsule written in OCTAVE which calculates the current and transconductances (gm, gmd and gms) using the charge based approach introduced in [1]. The capsule generates graphs demonstrating model versus TCAD simulations. The user can use the capsule code to experiment and reproduce the results in the paper [1]. 
The capsule is provided at the IEEE explorer site under the "Code&Datasets" link. https://ieeexplore.ieee.org/document/8371530 / doi: 10.1109/TED.2018.2838101 
Or at the link below https://codeocean.com/capsule/8244803/tree"

FIG: IdVg and gmVg at Vd=10mV
REF:
[1] N. Makris, F. Jazaeri, J. Sallese, R. K. Sharma and M. Bucher, "Charge-Based Modeling of Long-Channel Symmetric Double-Gate Junction FETs—Part I: Drain Current and Transconductances," in IEEE Transactions on Electron Devices, vol. 65, no. 7, pp. 2744-2750, July 2018.
doi: 10.1109/TED.2018.2838101
Abstract: The double-gate (DG) junction field-effect transistor (JFET) is a classical electron device, with a simple structure that presents many advantages in terms of not only device fabrication but also its operation. The device has been largely used in low-noise applications, but also more recently, in power electronics. Physics-based compact models for JFETs, contrary to MOSFETs, are, however, scarce. In this paper, an analytical, charge-based model is established for the mobile charges, drain current, and transconductances of symmetric DG JFETs, covering all regions of device operation. The model is unified and continuous from subthreshold to linear and saturation operation and is valid over a large temperature range. This charge-based model constitutes the basis of a full compact model of the DG JFET.
Keywords: junction gate field effect transistors;semiconductor device models;mobile charges;double-gate junction field-effect transistor;classical electron device;low-noise applications;power electronics;long-channel symmetric double-gate junction FET;symmetric DG JFET;charge-based modeling;physics-based compact models;drain current;Electric potential;JFETs;Logic gates;Integrated circuit modeling;Junctions;Mathematical model;MOSFET;Analytical model;circuit simulation;compact model;junction field-effect transistor (JFET);temperature effect



[paper] A Surface-Potential-Based Analytical I-V Model of Full-Depletion Single-Gate SOI MOSFETs

1
Department of Electrical and Electronic Teaching, 
College of Information Science and Engineering, 
Huaqiao University, Xiamen 361021, China

2
Department of Electronic Engineering, Jinan University, Guangzhou 510632, China
*
Correspondence: yufei_jnu@126.com; Tel.: +86-0592-6162-385
These two authors contributed equally to this work.

Received: 10 May 2019 / Accepted: 12 June 2019 / Published: 14 July 2019
Electronics 20198(7), 785; https://doi.org/10.3390/electronics8070785

Abstract

: 
A surface-potential-based analytical I-V model of single-gate (SG) silicon-on-insulator (SOI) MOSFETs in full-depletion (FD) mode is proposed and compared with numerical data and Khandelwal’s experimental results. An explicit calculation scheme of surface potential, processing high computation accuracy and efficiency, is demonstrated according to the derivation of the coupling relation between surface potential and back-channel potential. The maximum absolute error decreases into 10−7 V scale, and computation efficiency is improved substantially compared with numerical iteration. Depending on the surface potential, the drain current is derived in closed-form and validated by Khandelwal’s experimental data. High computation accuracy and efficiency suggest that this analytical I-V model displays great promise for SOI device optimizations and circuit simulations.

Keywords:
 silicon-on-insulator MOSFETs; surface potential; back-channel potential; full-depletion; analytical I-V model
Figure 1. x-y cross section of silicon-on-insulator (SOI) MOSFETs.