Modeling Emerging Semiconductor Devices for Circuit Simulation https://t.co/QMvNfZ9vsl #paper https://t.co/1gWFMFxzmq

Modeling Emerging Semiconductor Devices for Circuit Simulation https://t.co/QMvNfZ9vsl #paper pic.twitter.com/1gWFMFxzmq

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[paper] Novel General Compact Model Approach

A Novel General Compact Model Approach for 7nm Technology Node Circuit Optimization from Device Perspective and Beyond

Qiang Huo, Zhenhua Wu, Weixing Huang, Xingsheng Wang, Senior Member, IEEE, Geyu Tang, Jiaxin Yao, Yongpan Liu, Feng Zhang, Ling Li, and Ming Liu, Fellow,IEEE

Abstract: This work presents a novel general compact model for 7nm technology node devices like FinFETs. As an extension of previous conventional compact model that based on some less accurate elements including one-dimensional Poisson equation for three-dimensional devices and analytical equations for short channel effects, quantum effects and other physical effects, the general compact model combining few TCAD calibrated compact models with statistical methods can eliminate the tedious physical derivations. The general compact model has the advantages of efficient extraction, high accuracy, strong scaling capability and excellent transfer capability. As a demo application, two key design knobs of FinFET and their multiple impacts on RC control ESD power clamp circuit are systematically evaluated with implementation of the newly proposed general compact model, accounting for device design, circuit performance optimization and variation control. The performance of ESD power clamp can be improved extremely. This framework is also suitable for pathfinding researches on 5nm node gate-all-around devices, like nanowire (NW) FETs, nanosheet (NSH) FETs and beyond.

Index Terms: General compact model, FinFET, ESD power clamp, 7 nm technology node and beyond.

Fig. (A) The schematic of partial parameters of FinFET. (B) Key design rules of 7nm node FinFET as according to [1]. 

Access: https://arxiv.org/ftp/arxiv/papers/1905/1905.11207.pdf

REF: [1] S. Narasimha et al.“A 7nm CMOS technology platform for mobile and high performance compute application,” IEEE International Electron Devices Meeting (IEDM), Dec. 2017, pp. 29.5.1-29.5.4, doi: 10.1109/IEDM.2017.8268476.

[paper] Analogue and RF performances of Fully Depleted SOI MOSFET

Jean-Pierre Raskin¹

¹Institute of Information and Communication Technologies, Electronics and Applied Mathematics (ICTEAM), Université catholique de Louvain (UCLouvain), Place du Levant, 3, Maxwell Building, bte L5.04.04, office B.327, B-1348 Louvain-la-Neuve, Belgium

jean-pierre.raskin@uclouvain.be

ABSTRACT. Performance of RF integrated circuit (IC) is directly linked to the analogue and high frequency characteristics of the transistors, the quality of the back-end of line process as well as the electromagnetic properties of the substrate. Thanks to the introduction of the trap-rich high-resistivity Silicon-on-Insulator (SOI) substrate on the market, the ICs requirements in term of linearity are fulfilled. Today Partially Depleted (PD) SOI MOSFET is the mainstream technology for RF SOI systems. Future generations of mobile communication systems will require transistors with better high frequency performance operating at lower power consumption and in the millimeter-waves range. Fully Depleted (FD) SOI MOSFET is a quite promising candidate for the development of these future wireless communication systems. Most of the reported data on FD SOI concern their digital performance. In this paper, their analogue/RF behaviour is described and compared with bulk MOSFETs. Self-heating issue, non-linear behaviour as well as high frequency performance at cryogenic temperature for FD SOI MOSFET are discussed. Finally, a brief summary of the published RF and millimeter-waves ICs based on FD SOI technology is presented.

KEYWORDS. Silicon-on-Insulator (SOI), Fully Depleted (FD), high frequency behaviour, Radio Frequency (RF), millimeter-waves, analogue/RF performances, self-heating, non-linear behaviour, cryogenic temperature, Integrated Circuits (ICs).

FIG: Simplified cross section of FD SOI nMOSFET with back-gate (BGN).

ACCESS: http://www.openscience.fr/IMG/pdf/iste_componano19v2n1_5.pdf

As IEEE enters U.S/Huawei fray, Chinese editorial board member resigns https://t.co/piWApiqC0F #paper

As IEEE enters U.S/Huawei fray, Chinese editorial board member resigns https://t.co/piWApiqC0F #paper

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#Taiwan #Startup Plan Emulates #MIT, #Stanford https://t.co/BIMmAKI9iu #paper https://t.co/w1Qvi0LmT7

#Taiwan #Startup Plan Emulates #MIT, #Stanford https://t.co/BIMmAKI9iu #paper pic.twitter.com/w1Qvi0LmT7

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