Postdoctoral positions in device modeling in Spain

As Professor in the in the Department of Electronic Engineering in the Universitat Rovira i Virgili (URV), in Tarragona, Spain., I am going to apply for a postdoctoral position (funded by the Spanish Ministry) related to modeling (in particular compact modeling) and/or parameter extraction of emerging devices we are targeting, such as Multi-Gate MOSFETs, nanowire FETs ,GaN HEMTs, Tunnel FETs, organic and metal oxide TFTs and hyLEDs.

The candidate should be a person who holds a PhD as awarded after January 1 2014.

Contracts will have a duration of two years are expected to start after June 2019.
The candidate should have enough research experience in the field of semiconductor devices, and must have a very good knowledge of the physics of electron devices. The research project to be carried out can be adapted to the candidate's profile. 

The NEPHOS group at URV is one of the most powerful teams in Europe in the area of compact modeling of semiconductor devices.

 

Interested applicants should send me their CV by e-mail.
DEADLINE TO RECEIVE APPLICATIONS: January 24 2019

MY E-MAIL ADDRESS IS: benjamin.iniguez@urv.cat

Tarragona is a medium city (100000 inhabitants) with a Mediterranean climate and many recreation opportunities (nice beaches, theme parks, nature preserves, mountain hiking, touristic resorts and facilities). It is located 100 km Southwest of Barcelona, and it is very well connected by train, bus, highways and even low cost flights from its own airport. Additional information about the University and the department can be found at: www.urv.cat

 
Benjamin Iñiguez

 

 

 

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An Empirical Model to Enhance the Flexibility of gm/Id Tuning in BSIM-BULK Model

Ravi Goel, Chetan Gupta, Yogesh S. Chauhan

EE Department, Indian Institute of Technology Kanpur, Kanpur, India

Published in: 2018 5th IEEE Uttar Pradesh Section International Conference on Electrical, Electronics and Computer Engineering (UPCON)

Abstract: Recent enhancement in BSIM-BULK (formerly BSIM6) model is presented in this work. The industry standard models like BSIM4, PSP, BSIM-BULK etc. lack the parameters for tuning of transconductance to channel current ratio (gm/Id). gm/Id is also a critical figure of merit for analog applications. Here, we propose an empirical model to enhance the flexibility of gm/Id tuning behavior. The proposed model provides good fitting for different channel lengths and drain bias.

Paper Sections:
I. Introduction
II. An Empirical Model for gm/Id Tuning
III. Model Implementation
IV. Model Validation with TCAD
V. Conclusion

Source:
DOI: 10.1109/UPCON.2018.8597065

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Compact Transcapacitance Model for Short Channel DG FinFETs

Armenian Journal of Physics, vol. 11, issue 4, pp. 269-272

(Proceedings of the Int. Conference on Microwave and THz Technologies and Wireless Comm.)

Ashkhen Yesayan

Institute of Radiophysics and Electronics

Alikhanian Brothers str. 1, 0203 Ashtarak, Armenia

Received 15 November 2018

Abstract: A compact capacitance model is developed accounting for small-geometry effects in FinFETs. While decreasing the channel length, the transcapacitance model becomes very sensitive to all short channel effects, both in moderate and strong inversion regimes. In addition, for short channel devices, we need to take into account the inter-electrode capacitive coupling in the subthreshold regime, which is not significant for long channel devices. The quantum mechanical effects, which are very significant for thin Fins, are included in the model. The effect of mobility degradation on C-V characteristics is also demonstrated. The model was validated with numerical 3D Atlas simulations and a good accuracy of the model has been demonstrated in all operating regimes.

References:

[1] Tech. rep., International technology roadmap for semiconductor (ITRS). 2009.

[2] J.-M. Sallese, F. Krummenacher, F. Pregaldiny, C. Lallement, A. Roy, C. Enz, A design oriented charge-based current model for symmetric DG MOSFET and its correlation with the EKV formalism, Solid-State Electron, vol. 49 no. 3, pp. 485–489. 2005.

[3] A Yesayan, F Prégaldiny, N Chevillon, C Lallement, JM Sallese, Physics-based compact model for ultra-scaled FinFETs, Solid-State Electronics, vol. 62, no1, pp. 165-173, 2011.

[4] Liang X, Taur Y., A 2-D analytical solution for SCEs in DG MOSFETs. IEEE Trans Electron Dev 2004;51(9):1385–91.

[5] Ward D, Dutton R. ,A charge-oriented model for MOS transistor capacitances. IEEE J Solid-State Circ, 1978;13(5):703–8.

[6] Tang M. Etude et modélisation compacte du transistor FinFET. Ph.D. Thesis, University of Strasbourg; December 2009.

[7] Borli H, Vinkenes K, Fjeldly T., Physics-based capacitance modeling of short-channel double-gate MOSFETs. Phys Status Solidi (c) 2008;5(12):3643–6.

[8] Arora N., MOSFET models for VLSI circuit simulation. New York: Theory and Practice, Springer-Verlag; 1993, ISBN:3-211-82395-6

Source:

http://ajp.asj-oa.am/1004/1/EL_4.pdf