#Julia Co-Creators To Receive 2019 James H. Wilkinson #Prize for #Numerical #Software https://t.co/5oLiWnuDZL #opensource

#Julia Co-Creators To Receive 2019 James H. Wilkinson #Prize for #Numerical #Software https://t.co/5oLiWnuDZL #opensource

— Wladek Grabinski (@wladek60) January 9, 2019

from Twitter https://twitter.com/wladek60

January 09, 2019 at 08:12AM
via IFTTT

IEEE TED SI on Compact Modeling for Circuit Design

Special Issue on Compact Modeling for Circuit Design

Benjamin Iñiguez, Wladek Grabinski, Slobodan Mijalković, Kejun Xia, Andries J. Scholten, Yogesh Singh Chauhan, Ananda S. Roy, Sadayuki Yoshitomi, Kaikai Xu

in IEEE Transactions on Electron Devices, vol. 66, no. 1, Jan. 2019.

doi: 10.1109/TED.2018.2884284

Abstract: This Special Issue is dedicated to recent research in the field of compact modeling for circuit design. The topics included all device structures, provided it was demonstrated that the presented compact modeling solutions were implementable in circuit design tools. The last Special Issue addressing compact modeling of all types of semiconductor devices was published in 2006. Since then, new device structures, and with different materials, have emerged, and significant and successful research in compact advance device modeling has been done, as well in the application of compact models to circuit design. Therefore, a new Special Issue was needed that could include high-quality papers in these topics.

This Special Issue is dedicated to recent research in the field of compact modeling for circuit design. The topics included all device structures, provided it was demonstrated that the presented compact modeling solutions were implementable in circuit design tools. The last Special Issue addressing compact modeling of all types of semiconductor devices was published in 2006. Since then, new device structures, and with different materials, have emerged, and significant and successful research in compact advance device modeling has been done, as well in the application of compact models to circuit design. Therefore, a new Special Issue was needed that could include high-quality papers in these topics.

A total of 60 regular papers were submitted to this Special Issue, of which 21 were accepted. Besides, the Special Issue includes four invited papers. All papers, including the invited ones, were subjected to thorough peer review. A high number of reviewers have participated in this process. This has resulted in a Special Issue containing very high-quality papers.

The published papers target compact modeling aspects for a wide number of devices: several MOSFET structures, tunnel FETs, HEMTs, nanowire FETs, TMD FETs, TFTs, OLEDs, solar cells, photodiodes, and so on.Besides, different operation regimes and analyses are addressed: dc, RF, HV, ballistic regime, variability, reliability, aging, and so on.

The four invited papers also target different topics. The paper by C. C. McAndrew is focused on the successes and challenges of MOS compact models. S. Dongaonkar et al. address the opportunities and challenges of circuit design methodologies ranging from process corners to statistical circuit design. P. Zampardi et al. discuss the industrial view of III–V device compact modeling for circuit design. Finally, Madec et al. target a quite different and challenging environment for the modeling of biosensors, biosystems, and lab-on-chips.

I would like to thank the work done by the rest of the Editors of this Special Issue and also by all the reviewers who participated in this process. And of course, I want to thank all the authors for their interest in submitting papers to this Special Issue. Thanks to authors, reviewers, and editors, this high-quality Special Issue has been possible.

(stream now) Crowdfunding, #FOSDEM, cases, contributions and self-assembly https://t.co/WuZj64zQ92 #opensource

(stream now) Crowdfunding, #FOSDEM, cases, contributions and self-assembly https://t.co/WuZj64zQ92 #opensource

— Wladek Grabinski (@wladek60) December 30, 2018

from Twitter https://twitter.com/wladek60

December 30, 2018 at 08:03PM
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[mos-ak] [press note] 11th International MOS-AK Workshop, Silicon Valley, December 5, 2018

Modeling of Systems and Parameter Extraction Working Group

11th International MOS-AK Workshop

Silvaco Inc. Headquarters, Silicon Valley, December 5, 2018

Summary

The MOS-AK Compact Modeling Association, a global standardization forum for semiconductor device models, held its 11th MOS-AK Workshop at the Silvaco Inc. headquarters in Santa Clara, Calif. on December 5, 2018. The event was co-located with the 2018 IEEE International Electron Devices (IEDM) and the Q4 Compact Modeling Coalition (CMC) meetings. The workshop receives technical program co-sponsorship from the IEEE Santa Clara Valley-San Francisco Chapter of the Electron Devices Society, Europractice, IJHSES as well as NEEDS of nanoHUB.org.

Bogdan Tudor, Silvaco Inc. and Wladek Grabinski, MOS-AK, welcomed more than 30 international academic researchers and modeling engineers. The nine technical compact modeling presentations covered nanoscale technologies, semiconductor devices modeling and advanced IC design.

The MOS-AK speakers shared their latest perspectives on compact/SPICE modeling and Verilog-A standardization in response to the dynamically evolving semiconductor industry and academic R&D efforts. The event featured advanced technical presentations covering compact model development, implementation, and deployment. For more information about each of the presentations, including full abstracts, go online to MOS-AK Workshop Silicon Valley 2018.

The nine topics presented were the following:

1. Silvaco GaN HEMT Compact Modeling Perspective, Bogdan Tudor, Colin Shaw and Sungwon Kong, Silvaco, Inc.
2. GaN HEMT Devices and Modeling for Operational Electronics at Harsh Environments, Saleh Kargarrazi, XLab, Stanford University
3. Impact of Basal Plane Dislocations and Ruggedness of 10 kV 4H-SiC Transistors, Victor Veliadis, PowerAmerica, North Carolina State University
4. Direct measurement of white noise in MOSFETs, Kenji Ohmori, Device Lab Inc.
5. NEREID Technology Roadmap, Enrico Sangiorgi, NEREID, University of Bologna
6. A Physics-Based Compact Model of RRAM for Emerging Applications, Paolo Pavan, University of Modena and Reggio Emilia
7. From Physics to Power, Performance, and Parasitics, Oskar Baumgartner, Global TCAD Solutions GmbH
8. MOS-AK FOSS Compact Modeling Perspective, Wladek Grabinski, IEEE EDS DL, MOS-AK
9. Compact Model of Single TeraFET Spectrometer, Michael Shur, Rensselaer Polytechnic Institute

There were also presentations of Late News with the following topics:

1. CMC Developer Model Software Licenses, Peter Lee, Micron
2. Xyce Parallel Electronic Simulator (Ver. 6.10), Jason Verley, Sandia National Laboratories
3. Call for Papers for ESSDERC/ESSCIRC 2019 in Krakow, Wladek Grabinski, MOS-AK

Photo: Some of the participants of the 11th MOS-AK Workshop at Silvaco Inc. Headquarters in Silicon Valley.

The MOS-AK Association plans to continue its standardization efforts by organizing future compact modeling meetings, workshops and courses in India, China, Europe, USA and, for the very first time, in Latin America, throughout the coming year, including:

• FOSDEM CAD/EDA DevRoom Feb. 2-3, 2019, ULB Solbosch
• 1st MOS-AK at LAEDC Feb. 25-28, 2019, Armenia, Columbia
• 2nd MOS-AK India Conference Feb. 25-27, 2019, IIT Hyderabad
• 4th Sino MOS-AK Workshop Jun. 20-23, 2019, UECST Chengdu
• MIXDES Special CM Session June 27-29, 2019, Rzeszow
• ESSDERC/ESSCIRC Sept. 23-26, 2019, AHG Krakow

About Silvaco:
Silvaco, Inc. is a leading EDA tools and semiconductor IP provider used for process and device development for advanced semiconductors, power IC, display and memory design. For over 30 years, Silvaco has enabled its customers to develop next generation semiconductor products in the shortest time with reduced cost. We are a technology company outpacing the EDA industry by delivering innovative smart silicon solutions to meet the world's ever-growing demand for mobile intelligent computing. The company is headquartered in Santa Clara, California and has a global presence with offices located in North America, Europe, Japan and Asia.

About Europractice IC Service:
The EUROPRACTICE IC Service brings ASIC design and manufacturing capability within the technical and financial reach of any company that wishes to use ASICs. The EUROPRACTICE IC Service, offered by IMEC and Fraunhofer, offers low-cost ASIC prototyping and ASIC small volume production ramp-up to high volume production through Multi Project Wafer - MPW - and dedicated wafer runs.

About MOS-AK Association:
MOS-AK is an international compact modeling association primarily focused in Europe, to enable international compact modeling R&D exchange in the North/Latin Americas, EMEA and Asia/Pacific Regions. The MOS-AK Modeling Working Group plays a central role in developing a common information exchange system among foundries, CAD vendors, IC designers and model developers by contributing and promoting different elements of compact/SPICE modeling and its Verilog-A standardization and related CAD/EDA tools including FOSS for compact/SPICE model development, validation/implementation and distribution. For more information please visit mos-ak.org

[C4P] EuroSOI-ULIS April 1-3, 2019, Grenoble (F)

5th Joint International EUROSOI and ULIS Conference

at Minatec, Grenoble (F) 

on April 1-3, 2019

The Conference Committee hopes that you will actively participate by submitting high quality papers and will enjoy the conference. The Conference Technical Digest will be published by IEEE and will be available online through IEEE Xplore. The abstract submission deadline is January 15, 2019.

Invited Speakers:

• Dr. Ionut RADU, SOITEC : "SOI technology: from niche to mainstream applications"
• Dr. Anabela VELOSO, IMEC: "Nanowire for ultra-scaled, high-density logic and memory applications"
• Dr. Marc GAILLARDIN, CEA: "Radiation effects in innovative devices"
• Prof. Ru HUANG, Peking University: "Steep slope devices"

More information are provided in the attached 2nd C4P and on the Conference website