[mos-ak] [Workshop Program] 2nd Sino MOS-AK Workshop in Hangzhou June 29-30, 2017

2nd Sino MOS-AK Workshop
Hangzhou June 29-30, 2017
Workshop Program online http://www.mos-ak.org/hangzhou_2017/

 
Together with the Honorary Committee Chair LingLing Sun, HangZhou Dianzi University and International MOS-AK Board of R&D Advisers: Larry Nagel, Omega Enterprises Consulting (USA), Andrei Vladimirescu, UCB (USA); ISEP (FR) as well as the local coordinator Min Zhang, XMOD (Shanghai) and all the Extended MOS-AK TPC Members, we have pleasure to invite to the 2nd Sino MOS-AK Workshop in Hangzhou on June 29-30, 2017. The MOS-AK workshop is organized with aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to the compact/SPICE modeling and its Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors. 

Important Dates:

• 2nd Announcement - April 2017
• Final Workshop Program - June 2017
• 2nd Sino MOS-AK Workshop - June 29-30, 2017
• 1st Day MOS-AK Workshop
• 2nd Day MOS-AK Workshop

Venue:

会议场所：杭州电子科技大学科技馆
Hangzhou Dianzi University; Science & Technology Museum

Final Program of 2nd Sino MOS-AK Workshop is available online
http://www.mos-ak.org/hangzhou_2017/
http://www.xmodtech.cn/Agenda (local link)
Note: 
Above topic and time arrangement sequence could be with tiny variation due to presenter's personal reason
(演讲顺序可能有改变，敬请留意）

Online MOS-AK/Hangzhou Workshop Registration

http://www.xmodtech.cn/registration
(any related inquiries can be sent to register@mos-ak.org)

Postworkshop Publications:
Selected best MOS-AK technical presentation will be recommended for further publication
in a special issue of the International Journal of High Speed Electronics and Systems

Extended MOS-AK Committee

WG13062017

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Working Student in Power Management (Intel Munich)

Working Student in Power Management f/m

Job Description: You will be responsible for developing a tool framework to breakdown and manage the power consumption of the Power Management ICs across all projects. The so-called power KPIs Key Performance Indicator are indeed strategic data critical for the competitiveness of battery powered system likes mobiles phones, wearables, IoT devices. You will be part of an enthusiastic and international system engineering team located in Munich and will get in touch locally with several design and validation teams.

Your main tasks in this full time position will be to:
- Setup a new framework to manage the power data in a new tool and environment
- Migrate existing project power consumption specifications and measurements currently in Excel
- Measure and correlate power KPIs on engineering samples in the post-silicon lab.
- Validate current power modelling approach and propose further model optimizations
- Contribute to the reporting and documentation for other teams and management

[read more...]

A Guide to Creating Robust Device Models

Well-Posed Device Models for Electrical Circuit Simulation
A Guide to Creating Robust Device Models
A. Gokcen Mahmutoglu, Tianshi Wang, Archit Gupta and Jaijeet Roychowdhury
March 25, 2017

Synopsis: This document provides guidelines for creating computational device models that work well in simulation. We build our discussion around the mathematical notion of “well-posedness”. We show that the requirements for a model to be well-posed stem from the internal working mechanisms of simulators. Therefore, our main aim is to provide insight into the numerical procedures used by simulators in order to help model developers avoid ill-posedness issues. We start our discussion with an example that shows how an ill-posed Verilog-A model can produce different simulation results in different simulators. We then provide a step-by-step simulation case study. In this case study, we illustrate the role of device models in simulations by examining the steps a simulator goes through, from taking a netlist as input to producing a simulation result as output. Finally, we distill our discussion in a functional definition of a well-posed model. As an extension to our theoretical discussion, we also provide practical guidelines that should be followed by Verilog-A models in order to avoid ill-posedness issues.

This document is published as a part of the Nano-Engineered Electronic Device Simulation (NEEDS) initiative. NEEDS is an NSF-funded initiative whose charter includes the development of tools and techniques for the production of high-quality device models¹:

“NEEDS has a vision for a new era of electronics that couples the power of billion-transistor CMOS technology with the new capabilities of emerging nano-devices and a charter to create high-quality models and a complete development environment that enables a community of compact model developers.

NEEDS Team: Purdue, MIT, UC Berkeley, and Stanford.”

¹For more information about NEEDS please visit https://nanohub.org/groups/needs/
https://nanohub.org/resources/26200/download/well-posed_device_models-29453e4.pdf

[mos-ak] [C4P] IJHSES / MOS-AK Special Issue

The IJHSES Call for Papers

Special Issue on Advances in the Compact/SPICE Modeling

and its Verilog-A Standardization

Compact/SPICE models for circuit level simulation are essential element of supporting CAD/EDA tools for advanced integrated circuit designs. Rapid mainstream CMOS technology expansion and its scaling into the nanometer regime demands development of a fully physical as well as technology predictive compact/SPICE models for circuit simulation which provides adequate, full range DC, AC, RF, and noise characteristics and its geometry, bias, temperature scaling. These tasks becomes a major R&D challenge. Fast new technology nodes developments also impose new challenges on the compact/SPICE models maintenance and development as well as on its Verilog-A standardization for the model implementation, validation and dissemination.

Standard, core compact models should include and update noise/mismatch and reliability/variability models as well as proximity effects to adequately model nanoscale devices and technologies including nonclassical MOSFETs, multigate FinFETs and nanowire FETs partially/fully-depleted ultra thin body (UTB) SOI, and thin-film transistors (TFTs). High-frequency, high-voltage high-power, high-temperature devices have been extensively investigated, and their compact models to be reviewed, too. Heterogeneous integration opens a new perspectives to the CMOS platform to integrate different materials (III-V/Ge channel, organic and different source/drain injection mechanisms (Schottky-barrier, tunneling, junctionless FETs, and others) and new nonclassical devices, high GHz/THz range detectors, Bio/Med sensors, actuators, MEMS, among others, to support emerging device in future VLSI, IoT applications and beyond.

Therefore, there is an emerging need for an new special issue to review status, challenge and advancement in the compact/SPICE modeling for nanoscaled and emerging technologies as well as beyond. The IJHSES Editors seek original manuscripts for a special issue on advanced in the Compact/SPICE Modeling and its Verilog-A standardization.

Topics to be covered include the following, but are not limited to:

• Advances in semiconductor technologies and processing

• Compact Modeling (CM) of the electron devices

• Verilog-A language for CM standardization

• New CM techniques and extraction software

• FOSS TCAD/EDA modeling and simulation

• CM of passive, active, sensors and actuators

• Emerging Devices, TFT CMOS and SOI-based memory cells

• Organic, Bio/Med devices/technology modeling

• Microwave, RF device modeling, HV/Power device modeling

• Nanoscale CMOS devices and circuits

• Technology R&D, DFY, DFT and IC Designs

• Foundry/Fabless Interface Strategies

Paper Submission and Review Schedule:

• First call for papers:    April 2017

• Second announcement:    June 2017

• Special Issue Due:    Dec. 2017

IJHSES Editor-in-Chief	Co-Editors-in-Chiefs	Guest Editors
Michael Shur Rensselaer Polytechnic Institute (USA)	Wladek Grabinski MOS-AK Association (EU) Benjamin Iñiguez DEEEA, ETSE, URV (SP)	Jean-Michel Sallese EPFL Lausanne (CH) Daniel Tomaszewski ITE Warsaw (PL)

WG250417

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[mos-ak] [2nd Announcement and Call for Papers] 2nd Sino MOS-AK Workshop in Hangzhou (CN) June 29-30, 2017

2nd Sino MOS-AK Workshop  

  in Hangzhou (CN) June 29-30, 2017
     2nd Announcement and Call for Papers   

 
Together with Prof. LingLing Sun, HangZhou Dianzi University, the honorary MOS-AK workshop chair,  Dr. Min Zhang, XMOD (Shanghai), local workshop coordinator and International MOS-AK Board of R&D Advisers: Larry Nagel, Omega Enterprises Consulting (USA), Andrei Vladimirescu, UCB (USA); ISEP (FR) as well as all the Extended MOS-AK TPC Committee, we have pleasure to invite to the 2nd Sino MOS-AK Workshop which will be held at 会议场所：杭州电子科技大学科技馆 Hangzhou Dianzi University Science & Technology Museum on June 29-20, 2017 in Hangzhou (CN).

Planned MOS-AK workshop is organized with aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors. 

Important Dates:

• Preannouncement - March 2016
  
• Call for Papers - April 24 2017
  
• Final Workshop Program - June. 2017
  
• MOS-AK Workshop - June 29-30, 2017

Venue:

会议场所：杭州电子科技大学科技馆
Hangzhou Dianzi University Science & Technology Museum
Hangzhou (CN)

Topics to be covered include the following among other related to the compact/SPICE modeling :

• Compact Modeling (CM) of the electron devices
  
• Advances in semiconductor technologies and processing
  
• Verilog-A language for CM standardization
  
• New CM techniques and extraction software
  
• Open Source TCAD/EDA modeling and simulation
  
• CM of passive, active, sensors and actuators
  
• Emerging Devices, TFT, CMOS and SOI-based memory cells
  
• Microwave, RF device modeling, high voltage device modeling
  
• Nanoscale CMOS devices and circuits
  
• Technology R&D, DFY, DFT and reliability/ageing IC Designs
  
• Foundry/Fabless Interface Strategies
  

Invited Speakers (tentative list in alphabetic order)

• Eric Leclerc, UMC Foundry (F)
• Ling Li, Chinese Academy of Sciences (CN)
• Helmut Puchner, Cypress Semi (US)
• Paulius Sakalas, TU Dresden (D)
• Pete Zampardi, RFMD (US)
• Thomas Zimmer, Uni. Bordeaux (F)

Online MOS-AK Abstract Submission:
Prospective authors should submit abstract online

Manuscript submission deadline: 29th May 2017 (Monday)
Notification of Acceptance: 5th June 2017 (Monday)
Submission of final manuscript: 19th June 2017 (Monday)

(any related inquiries can be sent to abstrscts@mos-ak.org)

Online Workshop Registration

using online registration form

(any related inquiries can be sent to register@mos-ak.org)

Postworkshop Publications:
Selected best MOS-AK technical presentation will be recommended for further publication
in a special issue of the International Journal of High Speed Electronics and Systems

Extended MOS-AK Committee

WG240417

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