1-cent "lab on a chip" could save lives

Rahim Esfandyarpour, Stanford University, helped to develop a way to create a diagnostic "lab on a chip" for just a penny:
"I'm pretty sure it will open a window for researchers because it makes life much easier for them - just print it and use it," said Esfandyarpour. The results of this research were recently published in the journal Proceedings of the National Academy of Sciences [Source: Stanford Medicine]

[paper] Bipolar and MOS Transistors Under the Effect of Radiation

Measurements of the Electrical Characteristics of Bipolar and MOS Transistors

Under the Effect of Radiation

K. O. Petrosyants, L. M. SamburskiiI. A. KharitonovM. V. Kozhukhov

Meas Tech (2017) doi:10.1007/s11018-017-1100-z

ABSTRACT: The specific nature of the process of measuring the electrical characteristics of bipolar and metal-oxidesemiconductor (MOS) transistors subjected to the action of neutron, electron, and gamma irradiation is considered. An automated measurement system is developed. Examples illustrating the use of the system for investigations of the radiation hardness of transistors are presented and the parameters of SPICE models for use in circuit design (including SOI/SOS CMOS circuits with EKV-RAD macromodel) are determined.

Translated from Izmeritel’naya Tekhnika, No. 10, pp. 55–60, September, 2016 [read more...]

[call for papers] 2017 IEEE S3S Conference

Overview: This industry - wide event has gathered, for over 30 years, industry leaders and widely known experts, in a social - oriented environment. Our contributed papers and invited talks are focused on SOI Technology, Low - Voltage Devices/Circuits/Architectures, and 3D Integration. These 3 technologies will play a major role in tomorrow's industry as they enable application - tailored and Energy / Cost efficient circuit designs.

Important Dates

Paper Submission Deadline: May 22, 2017

Acceptance Notification: July 1, 2017

The conference at a glance

Monday to Wednesday, Oct. 16-18, 2017: Technical Sessions

Thursday, Oct.19: Fully - Depleted SOI Circuit Design; Full-day Tutorial
Tuesday, Oct.17: Monolithic 3D Half-day Tutorial

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Scope: We welcome papers in the following areas:
Silicon On Insulator (SOI)
• Advanced Materials, Substrate and Processes • Device Physics, Characterization and Modeling • Device/Circuit Integration • SOI Design, Circuits and Applications	• Non-Digital Devices and Applications (RF, HV, Photonics, NEMS, MEMS, Analog...) • New SOI Structures, Circuits and Applications
Low-Voltage Microelectronics
• Space-Based and Unattended Remote Sensors • Biomedical Devices • Low-Voltage Handheld/wireless systems • Ultra-Low-Power Digital Computation • Analog and RF Technologies	• Low Voltage Memory Technologies • Energy Harvesting Techniques • Asynchronous Circuits • Novel Device and Fabrication Technology
3D Integration
• Low Thermal Budget Processing • Fabrication Techniques and Bonding Methods • Design and Test Methodologies • Processes for Multi Wafer Stacking • 3D IC EDA and Design Technology	• Heterogeneous Structures • 3D Manufacturing and Logistics • Reliability of 3D Circuits • Fault Tolerant 3D Designs

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Paper Submission:
Prospective authors should prepare a 2page abstract (follow online guidelines).
Acceptance is based on paper’s technical quality and relevance.

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Conference manager contact Joyce Lloyd
6930 De Celis Pl., #36
Van Nuys, CA 91406
Tel: +1 818 795 3768
Fax: +1 818 855 8392

HiSIM-HV and HiSIM2 implemented into ngspice

ngspice (Open Source SPICE Circuit Simulator) supports latest versions of HiSIM_HV and HiSIM2 [read more...]
REF: 

[1] HiSIM 2. Y. Z: Surface-Potential-Based RF MOSFET Model for Circuit Simulation

[2] T. Ezaki, D. Navarro, Y. Takeda, N. Sadachika, G. Suzuki, M. Miura-Mattausch, H. Mattausch, T. Ohguro, T. Iizuka, M. Taguchi, S. Kumashiro, and S. Miyamoto, “Non-quasi-static Analysis with HiSIM, a Complete Surface-potential-based MOSFET Model”, Proceedings of the 12 th International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES’2005), 923-928 (2005.6), Invited Paper

[3] M. Miura-Mattausch, D. Navarro, Y. Takeda, H.J. Mattausch, T. Ohguro, T. Iizuka, M. Taguchi and S. Miyamoto, “MOSFET Modeling for RF Circuit Era”, Proceedings of the 11 th International Conference on Mixed Design Mixed Design of Integrat ed Circuits and Systems (MIXDES’2004), 62-66 (2004), Invited Paper

[4] HiSIM_HV Y. Z: Surface-Potential-Based HV/LD_MOSFET Model for Circuit Simulation

[5] Mattausch,  H.J.;  Umeda,  T.;  Kikuchihara,  H.;  Miura-Mattausch,  M.,  "The  HiSIM compact models of high-voltage/power semiconductor devices for circuit simulation," in Solid-State and Integrated Circuit Technology (ICSICT), 2014 12th IEEE International Conference on , vol., no., pp.1-4, 28-31 Oct. 2014
[6] Mattausch,  H.J.;  Miyake,  M.;  Ii zuka,  T.;  Kikuchihara,  H.;  Miura-Mattausch,  M.,  "The Second-Generation  of  HiSIM_HV  Compact  Models  for  High-Voltage  MOSFETs,"  in Electron Devices, IEEE Transactions on , vol.60, no.2, pp.653-661, Feb. 2013

[paper] Model for Organic Thin-Film Transistor

Physically Based Compact Mobility Model for Organic Thin-Film Transistor

T. K. Maiti, L. Chen, H. Zenitani, H. Miyamoto, M. Miura-Mattausch and H. J. Mattausch

in IEEE Transactions on Electron Devices, vol. 63, no. 5, pp. 2057-2065, May 2016.

doi: 10.1109/TED.2016.2540653

Abstract: A physically based compact mobility model for organic thin-film transistors (OTFTs) with an analysis of bias-dependent Fermi-energy (EF) movement in the bandgap (Eg) is presented. Mobility in the localized and extended energy states predicts the drain-current behavior in the weak and strong accumulation operations of OTFTs, respectively. A hopping mobility model as a function of the surface potential is developed to describe the carrier transport through localized energy states located inside Eg. The Poole-Frenkel parallel-field-effect mobility and vertical-field-effect mobility are considered to interpret the bandlike carrier transport in the extended energy states. The parallel field effect on mobility is more pronounced for shorter channel length OTFTs and is considered by developing a channel-length-dependent mobility model. The vertical field effect on mobility is included to account for the effect of mobility on carrier transport at high gate-voltage-induced fields. We also compared the model results with 2-D device simulations and measurements to verify the developed mobility model [read more...]