Tin Oxide: The First Stable p-type #2D #Semiconductor Material https://t.co/mKQ9vHsbrJ #papers #feedly

Tin Oxide: The First Stable p-type #2D #Semiconductor Material https://t.co/mKQ9vHsbrJ #papers #feedly

— Wladek Grabinski (@wladek60) February 18, 2016

from Twitter https://twitter.com/wladek60

February 18, 2016 at 07:59AM
via IFTTT

#TFETs may #challenge MOSFETs https://t.co/9tyWFYJprp #cad #feedly #papers

#TFETs may #challenge MOSFETs https://t.co/9tyWFYJprp #cad #feedly #papers

— Wladek Grabinski (@wladek60) February 10, 2016

from Twitter https://twitter.com/wladek60

February 10, 2016 at 12:46PM
via IFTTT

Obama makes risky bid to increase #science #spending https://t.co/ckzMvs97eb #papers #feedly

Obama makes risky bid to increase #science #spending https://t.co/ckzMvs97eb #papers #feedly

— Wladek Grabinski (@wladek60) February 10, 2016

from Twitter https://twitter.com/wladek60

February 10, 2016 at 07:57AM
via IFTTT

MIXDES 2016 Paper Submission Deadline

MIXDES Paper Submission Deadline
(March 1st, 2016)

---------- Forwarded message ----------
From: MIXDES 2016 Organizing Committee

Dear Colleagues,

I would like to kindly remind you that paper submission for MIXDES 2016 Conference has been already opened. The deadline for regular paper submission is March 1st, 2016, so I encourage you to register your papers. The instruction for paper preparation is available online. Please note that the paper format and content may be still updated up to Final Paper Version deadline (May 31st, 2016).

This year the MIXDES 2016 Conference will take place in Lodz, Poland, June 23-25, 2016. For more information regarding the conference please visit the MIXDES 2016 Conference web site at
www.mixdes.org.

If you have any questions please do not hesitate to contact me.

Hoping to see you in Lodz,

Mariusz Orlikowski
Secretary of the 23rd International Conference
"Mixed Design of Integrated Circuits and Systems"
MIXDES 2016
http://www.mixdes.org

Device to GDSII for IC Design Training

Hands on Training Program on “Device to GDSII for IC Design”

on 22-27 Feb 2016

Organized by VLSI Division of School of Electronics Engineering

Vellore Institute of Technology, Near Katpadi Rd Vellore, Tamil Nadu - 632014

The relentless march fast of the CMOS has slowed down and the semiconductor industry is looking for novel and innovative devices. Many novel devices are being explored currently. TCAD and Cadence tool allows us to generate new structures, circuits and analyze its performance. Unlike other circuit simulators, TCAD and Cadence needs a special training. This hands on training addresses this gap.

Target Audience: Faculty, students and research scholars from various engineering colleges of India. The number of participants is limited to 40. 

Topics to ďe addressed:

Using TCAD:

• Structure Creation, Simulation and Device Simulation 
• Process Simulation 
• Multi-gate Transistors 
• Radiation study on devices and circuits

Using Cadence: 

• RTL Design and Simulation 
• Synthesis and low power synthesis Using RTL Compiler 
• Physical aware synthesis and DFT 
• Block and Top Level P&R Using SOC Encounter 
• STA Using Timing Engine 

[read more...]