Jan 15, 2014

[Final Program] 11th International Workshop on Compact Modeling

11th International Workshop on Compact Modeling (IWCM 14)

January 23 (Thursday), 2014

Suntec Singapore Convention and Exhibition Centre (Room 309)

Workshop Program

9:00-9:10am Welcome address
Mansun Chan (workshop chair)

Session I: Modeling for Compact Semiconductor
Session Chair: Lining Zhang

9:10-9:35am Challenges and Prospects of Compact Modeling for Future Generation III-V/Si Co-integrated ULSI Circuit Design
Xing Zhou, Siau Ben Chiah, Binit Syamal, Hongtao Zhou, Arjun Ajaykumar, and Xu Liu; Nanyang Technological University, Singapore
9:35-10:00am A Large Signal Model for InP/InGaAs Double Heterojunction Bipolar Transistors
Yan Wang and Yuxia Shi; Tsinghua University, China
10:00-10:25am Analytical Modeling for AlGaN/GaN HEMTs
Aixi Zhang, Lining Zhang, Zhikai Tang, Xiaoxu Cheng*, Yan Wang*, Kevin J. Chen, and Mansun Chan; The Hong Kong University of Science and Technology, Hong Kong, China; *Tsinghua University, China

10:25-10:40am Break

Session II: Non-Classical Device Modeling and Platform
Session Chair: Xing Zhou

10:40-11:05am Developing i-MOS as a Compact Model Standardization Platform
Lining Zhang and Mansun Chan; The Hong Kong University of Science and Technology, Hong Kong, China
11:05-11:30am An Analytic Model for Nanowire Tunnel-FETs
Ying Liu, Jin He, Mansun Chan*, Caixia Du**, Yun Ye, Wei Zhao, Wen Wu and Wenping Wang; Peking University Shenzhen SOC Key Laboratory, China; *The Hong Kong University of Science and Technology, Hong Kong, China; **Shenzhen Huayue Teracale Chip Electronic Limited Co., China
11:30-11:55am A Channel Potential Based Model for SiO2- Core Si-Shell SRGMOSFET
Xiangyu Zhang, Jin He, Mansun Chan*, Caixia Du**, Yun Ye, Wei Zhao, Wen Wu and Wenping Wang; Peking University Shenzhen SOC Key Laboratory, China; *The Hong Kong University of Science and Technology, Hong Kong, China; **Shenzhen Huayue Teracale Chip Electronic Limited Co., China

11:55am-2:00pm Lunch

Session III: Power Device Modeling
Session Chair: Young June Park

2:00-2:25pm Compact Modeling of the Reverse Recovery Effect in LDMOS Body Diode (Invited)
M. Miyake; Hiroshima University, Japan
2:25-2:50pm Compact Modeling of the SiC IGBT Including the Switching at High Temperature
K. Matsuura, M. Miura-Mattausch, M. Miyake and H. J. Mattausch; Hiroshima University, Japan
2:50-3:15pm Experimental Verification of Power MOSFET Model under Switching Operations
A. Saito, M. Miura-Mattausch, M. Miyake, T. Umeda and H.J. Mattausch; Hiroshima University, Japan

3:15-3:30pm Break

Session IV: Reliability Modeling
Session Chair: Jin He

3:30-3:55pm 3D Monte Carlo Reaction-Diffusion Simulation Framework to model Time Dependent Dielectric Breakdown in BEOL Oxide
Seong Wook Choi and Young June Park; Seoul National University, Korea
3:55-4:20pm Development of NBTI and Channel Hot Carrier (CHC) Effect Models and their Application for Circuit Aging Simulation
Chenyue Ma, Hans Jürgen Mattausch, Kazuya Matsuzawa*, Seiichiro Yamaguchi*, Teruhiko Hoshida*, Masahiro Imade*, Risho Koh*, Takahiko Arakawa* and Mitiko Miura-Mattausch; Hiroshima University, Japan; * Semiconductor Technology Academic Research Center, Japan
4:20-4:45pm Modeling of the Surface Charges on Au Electrode Including Pseudocapacitance
Jooseong Kwon, Intae Jeong, Sungwook Choi and Young June Park; Seoul
National University, Korea

4:45-4:55pm Closing Remarks
Hans Juergen Mattausch (workshop co-chair)

Jan 13, 2014

The FD-SOI Papers at IEDM ’13

Thanks to Adele HARS, we can share this post:

The FD-SOI Papers at IEDM ’13

Posted by Adele HARS on December 16, 2013
Tagged with 10nm, 14nm, 28nm, conference, design, FD-SOI, GlobalFoundries, Hitachi, IBM, Leti, manufacturing, R&D, Renesas, silicon-on-insulator, Soitec, ST, strain, Synopsys, U.Tokyo, UTBB FD-SOI was a hot topic at this year’s IEEE International Electron Devices Meeting (IEDM) (www.ieee-iedm.org), the world’s showcase for the most important applied research breakthroughs in transistors and electronics technology.
The FD-SOI papers featured high performance, low leakage, ultra-low power (0.4V), excellent variability, reliability and scalability down to the 10 nm node using thin SOI and thin BOX substrate. Performance boosters using high mobility materials such as thin strain Si, Ge, and III-V on-Insulator were also presented.
Brief summaries of the FD-SOI papers, culled from the Advance Program (and some of the actual papers) follow.
9.2 High Performance UTBB FDSOI Devices Featuring 20nm Gate Length for 14nm Node and Beyond (STMicroelectronics, Leti, IBM, Renesas, Soitec, GlobalFoundries)

This was the big paper reporting on ST’s flavor of high-performance FD-SOI (UTBB, which stands for ultra-thin-body-and-box) with 20nm gatelength, which target the 14nm node. In addition to excellent results, the paper demonstrated that “…FD-SOI reliability is superior to Bulk devices.”

[8] C. Auth, et al, VLSI, p.131, 2012 [9] C.-H. Jan, et al, IEDM, p.44, 2012

Specifically, the alliance reports, for the first time, on high performance UTBB FD-SOI devices with a gate length (LG) of 20nm and BOX thickness (TBOX) of 25nm, featuring dual channel FETs (Si channel NFET and compressively strained SiGe channel PFET). Competitive effective current (Ieff) reaches 630μA/μm and 670μA/μm for NFET and PFET, respectively, at off current (Ioff) of 100nA/μm and Vdd of 0.9V.

Excellent electrostatics are obtained, demonstrating the scalability of these devices to14nm and beyond. Very low AVt (1.3mV•μm) of channel SiGe (cSiGe) PFET devices is reported for the first time. BTI was improved >20% vs a comparable bulk device. The paper concludes with evidence of continued scalability to 10nm

and below.

“The effective current (Ieff), as a function of Ioff, is shown in Fig. 4. At Vdd=0.9V, NFET/PFET Ieff reach 630/670μA/μm at Ioff=100nA/μm, respectively. They are the best performing FDSOI CMOS devices reported so far, featuring non-strained Si channel NFET and strained SiGe channel PFET.”

7.3 Innovative ESD protections for UTBB FD-SOI Technology (STMicroelectronics, IMEP-LAHC)

ESD (electrostatic discharge) protection is often cited as a challenge in FD-SOI, and the ESD devices are typically put into a “hybrid” section of the chip, where the top silicon and insulator are etched away exposing the “bulk” silicon base wafer. In this paper, however, the ST-IMEP team presented FD-SOI ESD protection devices that achieve “remarkable performance in terms of leakage current and triggering control.” They demonstrate “ultra-low leakage current below 0.1 pA/μm and adjustable triggering (1.1V < Vt1 < 2.6V) capability. These devices rely on gate-controlled injection barriers and match the 28nm UTBB-FDSOI ESD design window by triggering before the nominal breakdown voltage of digital core MOS transistors.”

7.4 Comparison of Self-Heating Effect (SHE) in Short-Channel Bulk and Ultra-Thin BOX SOI MOSFETs: Impacts of Doped Well, Ambient Temperature, and SOI/BOX Thicknesses on SHE (Keio University, AIST)

This paper refutes those who say that the self-heating effect (SHE) is a bigger concern for SOI-based devices than bulk. The researchers investigated and compared bulk and SOI FETs including 6-nm ultra-thin (UT) BOX devices. They clarified, for the first time, that SHE is not negligible in bulk FETs, mainly due to a decrease in the thermal conductivity of the more heavily doped well. They found that the channel temperature of 6-nm UT BOX SOI FETs is close to that of bulk FETs at a chip temperature under operations. They then proposed a thermal-aware FD-SOI device design structure based on evaluated BOX/SOI thickness dependences of SHE. They concluded that SHEs in UTBB FETs with raised S/D and/or contact pitch scaling could be comparable to bulk FETs in deeply scaled nodes.

20.3 Gate-Last Integration on Planar FDSOI MOSFET: Impact of Mechanical Boosters and Channel Orientations (Leti, ST)

This paper presents the industry’s first “gate last” (GL) results for FD-SOI, with ultra-thin silicon body (3-5nm) and BOX (25nm). The team successfully fabricated transistors down to the 15nm gate length, with metal-last on high-k first (TiN/HfSiON). They thoroughly characterized the gate stack (reliability, work-function tuning on Equivalent Oxide Thickness EOT=0.85nm) and transport (hole mobility, Raccess) for different surface and channel orientations. They report excellent Ion, p=1020μA/μm at Ioff, p=100nA/μm at Vdd=0.9V supply voltage for <110> pMOS channel on (001) surface with in-situ boron doped SiGe Raised Source and Drain (RSD) and compressive CESL. They cite the high efficiency of the strain transfer into the ultra-thin channel (-1.5%), as evidenced by physical strain measurements by dark field holography.

12.4 UTSOI2: A Complete Physical Compact Model for UTBB and Independent Double Gate MOSFETs (ST, Leti)

Compact models of transistors and other elementary devices are used to predict the behavior of a design. As such, they are embedded in simulations like SPICE that designers run before actual manufacturing. In this paper, ST and Leti researchers presented a complete physical compact model called UTSOI2, which is dedicated to Ultra-Thin Body and Box FD-SOI technology, and is able to describe accurately independent double gate operation for sub-20nm nodes. It meets standard Quality and Robustness tests for circuit design applications.

12.5 Mobility in High-K Metal Gate UTBB-FDSOI Devices: From NEGF to TCAD Perspectives (Invited) (ST, Leti, U. Udine, Synopsys, Laboratoire Hubert Curien & Institut d’Optique, IBM)

This paper reviews important theoretical and experimental aspects of both electrostatics and channel mobility in High-K Metal Gate UTBB-FDSOI MOSFETs. With an eye toward optimization, the team presents a simulation chain, including advanced quantum solvers, and semi-empirical Technology Computer Assisted Design (TCAD) tools.

33.2 Suppression of Die-to-Die Delay Variability of Silicon on Thin Buried Oxide (SOTB) CMOS Circuits by Balanced P/N Drivability Control with Back-Bias for Ultralow-Voltage (0.4 V) Operation (LEAP, U. Tokyo)

SOTB is what Hitachi calls its flavor of FD-SOI. The researchers point out that small-variability transistors like SOTB are effective for reducing the operation voltage (Vdd). This paper proposes the balanced n/p drivability for reducing the die-to-die delay variation by back bias for various circuits. Excellent delay variability reduction by this n/p balanced control is demonstrated at ultra-low Vdd of 0.4 V.

2.8: Co-Integration of InGaAs n- and SiGe p-MOSFETs into Digital CMOS Circuits Using Hybrid Dual-Channel ETXOI Substrate (IBM)

ETSOI is IBM’s flavor of FD-SOI, and this paper is about FD-SOI devices using high mobility material for boosting performance. The presenters “demonstrate for the first time on the same wafer and on the same device level a dense co-integration of co-planar nano-scaled SiGe p-FETs and InGaAs n-FETs UTBB FETs. This result is based on hybrid substrates containing extremely-thin SiGe and InGaAs layers on insulators (ETXOI) using double bonding.” They showed a) that it could be done; b) it’s viable hybrid high-mobility dual-channel CMOS; c) it still supports back-biasing for Vt tuning.

5.2 Surface Roughness Limited Mobility Modeling in Ultra-Thin SOI and Quantum Well III-V MOSFETs (DIEGM – U. Udine)

As with the IBM paper (2.8) above, this paper is about FD-SOI devices using high mobility material for boosting performance. The abstract explains, “This paper presents a new model for surface roughness mobility accounting for the wave-function oxide penetration and can naturally deal with Hetero-Structure. Calibration with experiments in Si MOSFETs results in a r.m.s. value of the SR spectrum in close agreement with AFM and TEM measurements.” The simulated μSR in III-V UTB MOSFETs shows a weaker degradation at small channel thickness (T_w) than predicted by the T_6wlaw observed in UTB Si MOSFETs.

Please stay tuned for a subsequent ASN post that will cover the meeting’s SOI-FinFET, RF-SOI and advanced device papers. (The papers themselves are typically available through the IEEE Xplore Digital Libary within a few months of the conference.)

An Update on the OpenPDK for IC Design (by Daniel Payne)

IC designers use EDA tools to implement their logical and physical design, and these tools require foundry-specific information for:

Design Rule Checking (DRC)
Layout Versus Schematic (LVS)
Library Symbols
Parasitic EXtraction (PEX)

This foundry information is called a Process Design Kit or PDK for short. Now put yourself in the place of the foundry or IDM, and you want to support EDA tools from multiple vendors like: Cadence Design Systems, Mentor Graphics, Synopsys, Silvaco and Tanner EDA. That adds up to a lot of QA and PDK development effort to support so many EDA vendors and tools. There has to be an easier way to create PDKs instead of one vendor at a time.

Read more at the original source

Jan 10, 2014

[mos-ak] [2nd announcement] Spring MOS-AK Workshop in London

Spring MOS-AK Workshop in London

Together with the workshop host, Prof. Bal Virdee, Londonmet, FIET MIEEE, and Prof. Mike Brinson, Londonmet, as well as Extended MOS-AK/GSA TPC Committee, we have pleasure to invite to the spring MOS-AK Workshop in London

Venue:

London Metropolitan University

Graduate Centre

166-220 Holloway Road

London N7 8DB

Important Dates:

Call for Papers - Dec 2013
2nd Announcement - Jan. 2014
Final Workshop Program - Feb. 2014
MOS-AK Workshop - March 28-29 2014

R&D topics to be covered include the following:

Advances in semiconductor technologies and processing
Compact Modeling (CM) of the electron devices
Verilog-A language for CM standardization
New CM techniques and extraction software
CM of passive, active, sensors and actuators
Emerging Devices, CMOS and SOI-based memory cells
Microwave, RF device modeling, high voltage device modeling
Nanoscale CMOS devices and circuits
Technology R&D, DFY, DFT and IC Designs
Foundry/Fabless Interface Strategies

Abstract Submission:

Authors should submit an abstract using on-line MOS-AK submission form (any related enquiries can be sent to abstract@mos-ak.org)

Postworkshop publications:

selected best MOS-AK technical presentation will be recommended for further publication in a special issue of the International Journal of Numerical Modelling: Electronic Networks, Devices and Fields

Extended MOS-AK/GSA Committee

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Jan 6, 2014

[mos-ak] [on-line publications] 6th International MOS-AK Workshop Washington DC Dec.11, 2013

Recent, 6th International MOS-AK/GSA Workshop on Dec.11, 2013 in Washington DC was organized to discuss SPICE/compact modeling and its standardization with a freewheeling session to review modeling activities of the CMC, IEEE EDS CMTC, NEEDS NanoHub and MOS-AK Groups. The workshop's presentations are available on-line at <http://www.mos-ak.org/washington_dc_2013/>

Please also distribute further information about next MOS-AK related events among all who are interested in the SPICE/compact modeling:

IWCM at DAC ASP Singapore (SG) Jan. 23, 2014

http://www.ece.nus.edu.sg/stfpage/elehy/aspdac2014/

Q2 2014 MOS-AK London (UK) March'2014

http://www.mos-ak.org/london_2014/

MIXDES Lwow (UA) June 19-21, 2014

http://mixdes2014.lp.edu.ua/Mixdes3/tekst/view/special

Q3 MOS-AK at 44th ESSDERC / 40th ESSCIRC Venice (I) Sept. 26, 2014

http://www.mos-ak.org/venice_2014/

Already now, I am looking forward to meet you at one of our MOS-AK modeling events, soon.

-- with regards - wladek;
--

Arbeitskreis Modellierung von Systemen und Parameterextraktion
Modeling of Systems and Parameter Extraction Working Group
--
Over two decades of Enabling Compact Modeling R&D Exchange

http://www.mos-ak.org