Sedemos News

Apr 11, 2013

A single European semiconductor strategy is on its way...

From Solid-State Technology:

At the International Semiconductor Strategy Symposium (ISS Europe), the European semiconductor industry affirmed its ability to innovate. More than 170 top industry representatives agreed on a number of joint steps and strategic measures to strengthen their competitiveness and sustainability. The controversial question whether the best way to attack future challenges will be "More Moore" or "More than Moore," ended in an expected compromise, namely that the industry should pursuit both strategies concurrently, the participants of a panel expressed. Whilst the More than Moore sector is traditionally strong in Europe, going on with More Moore is important for two to three device makers in Europe and in particular for the European equipment suppliers which export 80% of their products.
In a global scale, the semiconductor industry is approaching the move to 450mm wafer processing technology – a step that promises to greatly boost the productivity of semiconductor manufacturers. However, since the investment to build a 450mm fab easily exceeds the 10 billion dollar mark, this move is regarded as risky and, for this reason, reserved to only the very largest enterprises. In the past, this perspective divided the European industry into two camps - the "More Moore" group that advocates taking on the 450mm challenge, and the "More than Moore" group which shunned this risky investment and preferred to rely on application-oriented differentiation instead.
At the event SEMI Europe, an industry association embracing enterprises that represent the entire value chain and organizer of the ISS Europe, set up a high-ranking panel discussion on options and choices of a single European semiconductor strategy. The panel proved that entrepreneurial spirit is well alive among Europe's chipmakers, technology suppliers and researchers.

Read more...

Apr 5, 2013

[mos-ak] CMC GaN HEMT Model Standardization Effort - Call for Candidate Models

Since its inception, the Compact Model Council (CMC) has collaborated to develop, maintain, and standardize compact models for widely used semiconductor components. CMC members have decided that gallium nitride (GaN) technology is important for their business and the CMC intends to develop its first standard GaN HEMT transistor model. More information about the CMC can be found in the attached document. The ability for the model to generalize from GaN to other III-V FETs would be a bonus but is not a requirement. After the CMC evaluates and standardizes a model for GaN HEMTs, the CMC may decide to extend this effort to all III-V FET/HEMT devices. We are currently soliciting candidate models for this standard.

GaN transistors are high electron mobility transistors (HEMTs), a FET technology based on a heterojunction channel and a Schottky / Insulated / Junction (pGaN) gate. The primary applications for GaN transistors are for high voltage / high power devices to be used as for example as switches; and for high frequency / high power devices to be used for example in RF power amplifiers.

The CMC plans a three-phase process for identification and evaluation of candidate models. We currently have started Phase I which is a solicitation of available models which meet the fundamental requirements set forth in the attached Requirements Document. The GaN Subcommittee will review written proposals and request top candidates to present an overview of their model at a CMC Meeting. Candidates identified in Phase I which have sufficient support from CMC sponsors will be subjected to thorough testing in subsequent Phases. All developers submitting a proposed standard to CMC for adoption will read and accept the CMC Standard Model Copyright Policy.

The attached document lists the model requirements and various types of measurements that the model must reproduce. They include IV curves over various bias and temperature conditions, high frequency measurements, switching measurements, and time dependent measurements to characterize trapping effects. The attached check-list should be used to identify which requirements are or will be met by the candidate model.

After a set of candidate models is obtained, Phase II starts with a set of measured data against which the models will be evaluated. This technology has not yet been decided. At this point the CMC will need brief documentation outlining the list of measurements and the data. The details of how the GaN devices are being fabricated, nor the details of their internal structure, will be required. A minimum set of device physical dimensions would be needed in order to feed candidate models with meaningful parameters, such as channel length, channel width, gate to source/drain contact distance, etc. The CMC GaN FET subcommittee will review the proposed measurement data and will determine which data set(s) will be used for model evaluation. It is possible that data from more than one source will be retained for the model evaluation, to cover an as wide as possible range of applications.

If you are aware of any organization willing to contribute, please forward this document, or contact the GaN FET subcommittee chair, Samuel Mertens (samuel_mertens(at)agilent.com). Don't hesitate to ask me any questions about the standardization process or the CMC.

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Apr 3, 2013

[mos-ak] [Final Program] Spring MOS-AK/GSA Workshop in Munich; April 11-12, 2013

Together with the workshop host, Prof. Dr. Doris Schmitt-Landsiedel, Lehrstuhl fur Technische Elektronik, TUM and Extended MOS-AK/GSA TPC Committee and the workshop sponsors MunEDA and Tanner EDA as well as the IEEE EDS Chapter Germany, the technical program cosponsor, we have pleasure to invite to the spring MOS-AK/GSA Workshop in Munich

Venue:

Lehrstuhl fur Technische Elektronik

Room: 5325, 5th floor <http://www.lte.ei.tum.de/index.html>

Technische Universitat Munchen

Arcisstr. 21 D-80333 Munchen

Registration: free on-line registration

MOS-AK/GSA Workshop Agenda

<http://www.mos-ak.org/munich_2013/>

April 11	Thursday, Afternoon Session
13:00 - 16:00	Oral presentations
	Welcome and Workshop Opening Wladek Grabinski; MOS-AK
	Statistical modeling with backward propagation of variance (BPV) and covariance equations Klaus-Willi Pieper and Elmar Gondro; Infineon Technologies
	Circuit Sizing: Corner Models Challenges & Applications Matthias Sylvester; MunEDA (D)
	Compact Modeling Activities in The Framework of the EU-Funded "COMON" Project Benjamin Iñiguez; URV, Tarragona (SP)
	Effective Device Modeling And Verification Tools Ingo Nickeleit; Agilent Technologies
16:00 - 17:00	Software/Hardware Demos
	MunEDA Framework Applications Tanner TSpice Verilog-A Agilent B1505A Power Device Analyzer / Curve Tracer
	Networking Evening Event
April 12	Friday, Sessions
9:00 - 12:00	Morning Oral Presentations
	Institute for Technical Electronics (LTE) Presentation Prof. Dr. rer. nat. Doris Schmitt-Landsiedel, LTE, TUM (D)
	STEEPER: Tunnel Field Effect Transistors (TFETs) Technology, Devices and Applications Thomas Schulz and Reinhard Mahnkopf, Intel, IMC, (D)
	Current and Future Challenges for TCAD Christoph Jungemann and Christoph Zimmermann; RWTH Aachen University (D)
	Advances in Verilog-A Compact Semiconductor Device Modeling with Qucs/QucsStudio Mike Brinson; London Metropolitan University, London, UK
12:00 - 13:00	Lunch
13:00 - 16:00	Afternoon Oral Presentations
	FDSOI Devices Bentchmarking Bich-Yen Nguyen; SOITEC (F)
	COMON: SOI Multigate Devices Modeling Alexander Kloes; THM (D)
	COMON: FinFET Modeling Activities Udit Monga; Intel, IMC, (D)
	COMON: HV MOS Devices Modeling Matthias Bucher; TUC, (GR)
	End of the Workshop

Committee: Extended MOS-AK/GSA Committee

Call for IJNM Papers: Modeling of high-frequency silicon transistors

Silicon transistors (STs) have been the workhorse of the electronics industry ever since its inception. Although STs historically have been used primarily in digital and low-frequency analog applications, they increasingly are being adopted for high-frequency analog purposes as well. This trend is fueled by the introduction of new fabrication methods, novel materials, and transistor architectures that permit aggressive downscaling into the nanometer regime. Along these lines, considerable attention currently is being devoted to the FinFET, which is an innovative multiple-gate field effect transistor offering the important advantage of being compatible with conventional planar CMOS technology.

Modeling and simulation are indispensable in the development of high-frequency STs. Indeed, ST models and simulations provide indispensable feedback for improving device fabrication processes and serve as a valuable tool for optimizing circuit designs. Unfortunately, the predictive power of modeling and simulation techniques for STs for digital and low-frequency applications oftentimes diminishes when applied to high-frequency analog STs. For modeling and simulation methods to drive the development of high-frequency ST technology, they must adapt as well.

The purpose of this Special Issue is to publish high-quality contributions addressing the modeling and simulation of high-frequency STs. A wide range of topics will be covered, ranging from bipolar to ?eld effect transistors and from linear to noise and non-linear models. Although the main focus of the Special Issue will be the extraction of high-frequency models, papers addressing other aspects of ST modeling will be considered as well. This issue will contain both invited and contributed papers. Manuscripts for this Special Issue should adhere to the requirements for regular papers of the IJNM as specified in the Author Guidelines at http://onlinelibrary.wiley.com/journal/10.1002/ (ISSN)1099-1204/homepage/ForAuthors.html.

Potential contributors may contact the Guest Editors to determine the suitability of their contribution to the Special Issue. All manuscripts should be submitted via the IJNM’s manuscript website http://mc.manuscriptcentral.com/ijnm, with a statement that they are intended for this Special Issue.

Guest Editors:

Dr. Giovanni Crupi
University of Messina, Italy
E-mail: crupig@unime.it
Prof. Dominique Schreurs
University of Leuven, Belgium
E-mail: dominique.schreurs@esat.kuleuven.be
Prof. Alina Caddemi
University of Messina, Italy
E-mail: acaddemi@unime.it

Manuscript submission deadline: April 30, 2013

Mar 19, 2013

[mos-ak] [2nd announcement] Spring MOS-AK/GSA Workshop in Munich; April 11-12, 2013

Together with the workshop host, Prof. Dr. Doris Schmitt-Landsiedel, Lehrstuhl fur Technische Elektronik, TUM and Extended MOS-AK/GSA TPC Committee and the workshop sponsors MunEDA and Tanner EDA, we have pleasure to invite to the spring MOS-AK/GSA Workshop in Munich <http://www.mos-ak.org/munich_2013/>

Venue:

Lehrstuhl fur Technische Elektronik

Room: 5325, 5th floor <http://www.lte.ei.tum.de/index.html>

Technische Universitat Munchen

Arcisstr. 21 D-80333 Munchen

Important Dates:

Call for Papers - Jan. 2013
2nd Announcement - March 2013
Final Workshop Program - March, 2013
MOS-AK/GSA Workshop - April 11-12, 2013

R&D topics to be covered include the following:

Advances in semiconductor technologies and processing
Compact Modeling (CM) of the electron devices
Verilog-A language for CM standardization
New CM techniques and extraction software
CM of passive, active, sensors and actuators
Emerging Devices, CMOS and SOI-based memory cells
Microwave, RF device modeling, high voltage device modeling
Nanoscale CMOS devices and circuits
Technology R&D, DFY, DFT and IC Designs
Foundry/Fabless Interface Strategies

Postworkshop publications;

selected best MOS-AK technical presentation will be recommended for further publication in a special issue of the International Journal of Numerical Modelling: Electronic Networks, Devices and Fields

Extended MOS-AK/GSA Committee