Job Offer for Compact Modeling (april, 2012)

Remember: we are only re-posting this information, and we're not related to the offer in any other form.

Device Modeling / Compact Modeling Lead / Manager

A top tier Research Group of Semiconductor MNC - Client of HanDigital - Bangalore (Bengaluru Area, India)

Job Description

• Manage and lead a strong technical team to effectively
• Develop compact models for FETs and passive devices like diodes, resistors, inductors , capacitors
• Design testsites and define test programs for RF/DCcharacterization
• Work closely with globally integrated team ofdevice modelers, technology developers and circuit designers
• Client interfacing to address concerns on device models, PDK or circuit performance.

Desired Skills & Experience

Experience : PhD with 10 to 12 Yrs / MS with 12 to 15 Yrs
 
Total Years of relevant experience :Minimum 5 or more years of experience in Device Modeling ; Hands-on experience with RF device / circuit design  and characterization.
 
Technical Knowhow required for the job

• Strong background in semiconductor device physics and characterization particularly in silicon platform is required
• Familiarity with industry standard BSIM or PSP models
• Experience with EDA tools like Cadence, Spectre, HSpice and ADS

Additional Details :

• Excellent written & oral communication skills
• Excellent Technical leadership skills
• Direct working experience with foundries ( Desired ,  Not a Mandatory )

Company Description

Our client is Bangalore based research center is responsible for the definition and development of industry leading technologies such as Copper Interconnect, Silicon onInsulator (SOI), High-Performance Logic-Based Embedded DRAM technologies, and SiGe for RF and analog applications, and high-k material technologies.
 
The research group is also the leading organization in defining the most advanced technologies forthe 45 nm and 22 nm nodes, including research in various aspects of Lithography, strained silicon, and Magnetic RAM (MRAM). The research center develops all of semiconductor technologies including SOI, Bulk CMOS, RFCMOS, HVCMOS,SiGe HBT BiCMOS, and nanodevice technologies.

Additional Information

Posted:

April 5, 2012

Type:

Full-time

Experience:

Mid-Senior level

Functions:

Research, Engineering, Design 

Industries:

Semiconductors 

Compensation:

Best in the Industry

Referral Bonus:

• Applicable

Employer Job ID:

Device / Compact Modeling Manager

Job ID:

2815431

Job Offer in SanDisk (april, 2012)

Remember: we are only re-posting this information, and we're not related to the offer in any other form.

IBIS Models Design Engineer

SanDisk - Bangalore, India (Bengaluru Area, India)

Job Description

In this position, the individual will work in the NAND Flash team to generate IBIS models for the NAND IO’s to be finally used by the internal System team & external customers. In this highly visible role you will perform the following duties:

• Develop IBIS models for the Legacy and DDR IO’s.
• Develop HSPICE models for Legacy and DDR IO’s.
• Interact with the US & the India team.
• Over a period of time develop a team for IBIS models.
• Develop an automated methodology on developing the models

Desired Skills & Experience

This position requires a Bachelor or Master Degree in Electrical/ (Micro) Electronics / VLSI Engineering or equivalent. 2 to 8 years of experience in IBIS models development for the complex Input/Output Buffers. Understanding about the functionality of complex IO’s.Should have deep understanding about HSPICE simulators & IBIS tools e.g Magma Silicon Smart. Excellent Team player.

Company Description

SanDisk Corporation is the global leader in flash memory cards - from research, manufacturing and product design to consumer branding and retail distribution. SanDisk's product portfolio includes flash memory cards for mobile phones, digital cameras and camcorders; digital audio/video players; USB flash drives for consumers and the enterprise; embedded memory for mobile devices; and solid state drives for computers. SanDisk is a Silicon Valley-based S&P 500 company, with more than half its sales outside the United States.

Additional Information

Posted:

April 4, 2012

Type:

Full-time

Experience:

Mid-Senior level

Functions:

Engineering 

Industries:

Semiconductors 

Job ID:

2809898

[mos-ak] C4P MOS-AK/GSA Dresden Workshop (April 26-27, 2012)

Together with the Fraunhofer IIS, local organizer and Extended MOS-AK/GSA TPC Committee, we have pleasure to invite to the MOS-AK/GSA Dresden Workshop at Fraunhofer IIS, Zeunerstraße 38, D-01069 Dresden on April 26-27, 2012; with XFAB visit and networking event.

On-Line free registration is open:

http://mos-ak.org/dresden/registration.php

MOS-AK/GSA Meetings are organized with aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/Spice modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD tool vendors. Topics to be covered include the following:

 * Advances in semiconductor technologies and processing

 * Compact Modeling (CM) of the electron devices

 * Verilog-A language for CM standardization

 * New CM techniques and extraction software

 * CM of passive, active, sensors and actuators

 * Emerging Devices, CMOS and SOI-based memory cells

 * Microwave, RF device modeling, high voltage device modeling

 * Nanoscale CMOS devices and circuits

 * Technology R&D, DFY, DFT and IC Designs

 * Foundry/Fabless Interface Strategies

Speakers tentative list (in alphabetic order) includes:

 * Klaus Gaertner, WIAS Berlin

 * Thomas Gneiting, Admos

 * Joachim Haase, Fraunhofer, IIS

 * Benjamin Iniguez, URV Tarragona

 * Wolfgang Mathis, Uni Hannover

 * Paolo Nenzi, Uni Roma

 * Andrej Rumiantsev, Cascade

 * Franz Sischka, Agilent

 * Jiri Slezak, On-Semi

 * Daniel Tomaszewski, ITE Warsaw

 * Dietmar Warning, Atmel

Intending participants and authors should also note the following deadlines:

 * Call for Papers - Mar. 30, 2012

 * Final Workshop Program - April 10, 2012

 * MOS-AK/GSA Workshop - April 26-27, 2012

On-Line abstracts submission is open:

http://www.mos-ak.org/dresden/abstracts.php

Further details and updates: <http://www.mos-ak.org/dresden> 

Email contact: <dresden@mos-ak.org>

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Introducing the 2012 IEEE Fellows

The IEEE Fellows class for 2012 has been announced on 5 March 2012. The Institute salutes these 329 IEEE senior members from around the world who have been named IEEE Fellows for 2012. They join an elite group of more than 6000 IEEE Fellows, who have contributed to the advancement or application of engineering, science, and technology.

2nd Training Course on Compact Modeling

Building on the success of its first edition in 2012, the 2nd Training Course on Compact Modeling (TCCM) will be held in Tarragona (Catalonia, Spain) on June 28-29 2012. It will be organized by will be organized by the NEPHOS Group, of the Department of Electronic, Electrical and Automatic Control Engineering at the Universitat Rovira i Virgili (Tarragona).. The General Chairman is Prof. Benjamin Iñiguez.

The Training Course on Compact Modeling will consist of 12 of lectures addressing relevant topics in the compact modeling of advanced electron devices. These lectures will be conducted by top experts in the field. Most of the lectures will target compact modeling issues applicable to many electron devices. In particular, emphasis will be given on MOSFETs (bulk, SOI, Multi-Gate and High Voltage MOS structures) and HEMTs.

The Training Course on Compact Modeling is an event sponsored by the FP7 “COMON” (COmpact MOdelling Network) IAPP Project (which is coordinated by the Universitat Rovira i Virgili) in collaboration with the IEEE EDS Compact Modeling Technical Committee.

The preliminary programme is already available at:

http://compactmodelling.eu/tccm2_programme.php

Prof. Raphaël Clerc (INPG, Grenoble, France)

"Tunnel and quasi-ballistictransport modelling in nanoscale MOS devices"

Prof. David Jiménez - Universitat Autònoma de Barcelona (UAB, Barcelona, Spain)

"Analytical quantum modelling of ultimate MOS devices"

Dr. Romain Ritzenthaler (IMEC, Belgium)

"3D analytical modelling techniques for Tri-Gate MOS structures"

Prof. Antonio Cerdeira (CINVESTAV,Mexico)

"Design-oriented compact modelling for Multi-Gate MOS devices"

Dr. Colin C. McAndrew (Freescale Semiconductors, Phoenix, AZ, USA)

"Statistical modelling techniques"

Dr. Thomas Gneiting (AdMOS GmbH, Frickenhausen, Germany)

"Flicker noise measurements and characterization"

Prof. Frédéric Martinez (Université de Montpellier 2, France)

"Low frequency noisemodeling"

Dr. Franz Sischka (Agilent Technologies, Böblingen, Germany)

"S-parameter and nonlinear RF modelling"

Prof. Giovanni Ghione (Politecnico di Torino, Italy)

"Thermal modelling of RF and microwave devices"

Prof. Jamal Deen (McMaster University, Canada)

"High frequencynoise modeling"

Prof. Mike Brinson (Metropolitan University of London, UK)

"QucsStudio: A second generation Qucs software package for compact semiconductor devicemodel development based on interactive and compiled equation-defined modellingtechniques plus circuit simulation"

Registration will be cheap, in particular before June 16 :

http://compactmodelling.eu/tccm2_registration.php

will include lunches, coffee breaks and a Gala Dinner on June 28, in a nice restaurant with TV screens to watch the Semifinals match of the Soccer European Cup ...

Besides, on June 25-27 the same group at URV will organize 8th International Conference on Organic Electronics (ICOE 2012) also in Tarragona. Participants to this Training Course will have a reduced fee for ICOE 2012.

I encourage compact modeling researchers to attend TCCM!