Sedemos News

Dec 1, 2011

Synopsys to Acquire Magma Design Automation

I copy from Synopsys site:

MOUNTAIN VIEW, Calif., Nov. 30, 2011 /PRNewswire/ -- Synopsys, Inc. (Nasdaq:SNPS), a world leader in software and IP used in the design, verification and manufacture of electronic components and systems, has signed a definitive agreement to acquire Magma® Design Automation Inc. (Nasdaq:LAVA), a provider of chip design software headquartered in San Jose, California. Bringing together complementary technology, development and support capabilities will enable the combined company to more rapidly meet customer requirements linked to chip designs at both leading-edge and mature process nodes.

Under the terms of the merger agreement, Synopsys will acquire Magma for $7.35 per Magma share in cash, resulting in a transaction value of approximately $507 million net of cash and debt acquired. The boards of directors of both companies have unanimously approved the transaction.

The closing of the merger is subject to customary conditions, including approval by the stockholders of Magma as well as U.S. regulators. In the event the merger closes as expected in the second calendar quarter of 2012, Synopsys anticipates it to be modestly accretive to non-GAAP earnings per share in its fiscal 2012. Synopsys plans to fund the acquisition with a combination of cash and debt, with the specifics to be determined at the time of close.

"The dramatic rise in complexity of today's semiconductor designs for all process nodes requires an equally dramatic increase in designer productivity. Customers are either dealing with the very complex physics of 20-nanometer design or they are squeezing the last bit of performance and cost from designs at mature, high-value nodes. To achieve success, our customers are asking for more new EDA capabilities than ever before," said Aart de Geus, chairman and CEO at Synopsys. "This acquisition will enable Synopsys to accelerate the delivery of the technology our customers need to keep the overall cost of design in check."

Nov 20, 2011

[mos-ak] Final Program MOS-AK/GSA Washington DC Workshop on Dec.7 2011

Final Program MOS-AK/GSA Washington DC Workshop on Dec.7 2011
====================================================
http://www.mos-ak.org/washington_dc/

* Free On-line Registration Form:
http://www.mos-ak.org/washington_dc/registration.php

* Venue:
The George Washington University Marvin Center
800 21st Street, Northwest, Suite 302
Washington, DC 20052
http://gwired.gwu.edu/marvincenter

* Agenda:
http://www.mos-ak.org/washington_dc/
With panel discussion:
Compact Model Verilog-A Standardization Panel
Geoffrey J. Coram, ADI (Moderator)
Marek Mierzwinski, Tiburon Design Automation (Introduction)
Panelists
Walter R. Curtice, WRC Consulting
Carlos Galup-Montoro UFSC, Brazil
Keith Green, TI, Compact Modeling Council
Benjamin Iniguez, URV, FP7 COMON Network

Local Organizing MOS-AK/GSA Committee:
======================================
Mona Zaghloul, GWU
Can E. Korman, GWU
John Suehle, NIST

Extended MOS-AK/GSA Committee:
==============================
Wladek Grabinski, GMC Suisse; MOS-AK/GSA Group Manager
Chelsea Boone, Director of Research GSA
* MOS-AK/GSA North America:
Chair: Pekka Ojala, Exar Corporation
Geoffrey Coram, Analog Devices
Jamal Deen, U.McMaster
Roberto Tinti, Agilent EEsof Division
* MOS-AK/GSA South America:
Chair: Gilson I Wirth; UFRGS; Brazil
Prof. Carlos Galup-Montoro, UFSC; Brazil
Sergio Bampi, UFRGS, Brazil
Antonio Cerdeira Altuzarra, Cinvestav - IPN, Mexico
* MOS-AK/GSA Europe:
Chair: Ehrenfried Seebacher, austriamicrosystems AG
Alexander Petr, XFab
Benjamin Iniguez, URV
James Victory, Sentinel-IC
* MOS-AK/GSA Asia/Pacific:
Chair: Goichi Yokomizo, STARC, Japan
Sadayuki Yoshitomi, Toshiba, Japan
A.B. Bhattacharyya, JIIT, India
Xing Zhou, NTU, Singapore

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Nov 11, 2011

[mos-ak] BSIM EKV Workshop at EPFL Lausanne on Dec. 15-16, 2011

Invitation to

The Nano-Tera Workshop on the Next Generation MOSFET Compact Models
15-16 December, 2011, EPFL

The BSIM group recently proposed BSIM6 as the new MOSFET compact model
to eventually replace BSIM3, BSIM4 and PSP for next generation bulk
CMOS processes. Trying to take advantage of the charge based features
of EKV, the BSIM research team from University of California,
Berkeley, led by Prof. Chenming Hu and the EKV modeling team at EPFL,
led by Prof. Christian Enz, decided to jointly develop the new BSIM6
compact model.

The BSIM EKV partnership has been officially announced by Profs. Hu
and Enz at the last ESSDERC-ESSIRC Conference during the MOS-AK
Workshop <http://mos-ak.org/helsinki/#BSIM-EKV>. The Nano-Tera
Workshop on the Next Generation MOSFET Compact Models will convene all
the BSIM and EKV researchers as well as the experts from the industry
to give an update on the latest status of BSIM6 and EKV (and
eventually other models as well) to the modeling and designer
community.

The detailed workshop program is available at: <http://ekv.epfl.ch/
workshop>

Oct 7, 2011

Space and time combine to overpower the human brain

Rich Goldman VP from Synopsys concluded that by the middle of this century, computing power will exceed the thinking capacity of all the humans beings on the planet.

For example, Goldman said, a 1982 Intel 80286 was 28 times more powerful than computers on the Voyagers 1 and 2, launched in 1977. Sputnik computers were capable of only 2,000 instructions per second. And a 2010 Apple iPad is 689 times more powerful than the onboard computers on the Columbia space shuttle, first launched in 1981. [read more]

Oct 4, 2011

[mos-ak] C4P MOS-AK/GSA Workshop in Washington DC on Dec. 7 2011

C4P MOS-AK/GSA Workshop in Washington DC on Dec. 7 2011
-------------------------------------------------------
http://www.mos-ak.org/washington_dc/
-------------------------------------------------------
Together with the Organizing Committee and Extended MOS-AK/GSA TPC
Committee, we have pleasure to invite to the MOS-AK/GSA Workshop in
Washington DC on Dec. 7 2011

The MOS-AK/GSA Workshop is HiTech forum to discuss the frontiers of
the electron devices modeling with emphasis on simulation-aware
models. Original papers presenting new developments and advances in
the compact/spice modeling and its Verilog-A standardization are
solicited. The main topics of the workshop are: (but are not limited
to):
* Compact Modeling (CM) of the electron devices
* VHDL-AMS/Verilog-A for CM standardization
* New CM techniques and extraction software
* CM of passive, active, sensors and actuators
* Emerging devices, CMOS and SOI-based memory cells
* Microwave, RF device modeling, high voltage device modeling
* Transistor Level IC support
* Nanoscale CMOS devices and circuits
* Reliability and thermal management of electron devices
* Technology R&D, DFY, DFT and IC designs
* Foundry/Fabless interface strategies

The terms of participation:
-------------------------------------------------------
Authors are asked to submit a short (~200words) abstract using on-
line
submission form by OCT.30 http://www.mos-ak.org/washington_dc
Intending authors should also note the following deadlines:
* Announcement and Call for Papers - Oct 2011
* on-line abstract submission deadline - OCT.30, 2011
* Final Workshop Program - Nov. 2011
* MOS-AK/GSA Workshop - Dec. 7, 2011
-------------------------------------------------------
Further details and updates and on-line workshop registration:
http://www.mos-ak.org/washington_dc
Email contact: washington_dc@mos-ak.org
-------------------------------------------------------