May 26, 2009

Engineers Discover Fundamental Flaw In Transistor Noise?

I copy here a part of a post in EDN (follow the link to get the full story... be aware that this seems to be quite yellowish press!!!):

According to the engineers at the National Institute of Standards and Technology (NIST) who discovered the problem, it will soon stand in the way of creating more efficient, lower-powered devices like cell phones and pacemakers unless we solve it.

While exploring transistor behavior, the team found evidence that a widely accepted model explaining errors caused by electronic "noise" in the switches does not fit the facts. A transistor must be made from highly purified materials to function; defects in these materials, like rocks in a stream, can divert the flow of electricity and cause the device to malfunction. This, in turn, makes it appear to fluctuate erratically between "on" and "off" states. For decades, the engineering community has largely accepted a theoretical model that identifies these defects and helps guide designers' efforts to mitigate them.

Those days are ending, says NIST's Jason Campbell, who has studied the fluctuations between on-off states in progressively smaller transistors. The theory, known as the elastic tunneling model, predicts that as transistors shrink, the fluctuations should correspondingly increase in frequency.

However, Campbell's group at NIST has shown that even in nanometer-sized transistors, the fluctuation frequency remains the same. "This implies that the theory explaining the effect must be wrong," Campbell said. "The model was a good working theory when transistors were large, but our observations clearly indicate that it's incorrect at the smaller nanoscale regimes where industry is headed."

The findings have particular implications for the low-power transistors currently in demand in the latest high-tech consumer technology, such as laptop computers. Low-power transistors are coveted because using them on chips would allow devices to run longer on less power—think cell phones that can run for a week on a single charge or pacemakers that operate for a decade without changing the battery. But Campbell says that the fluctuations his group observed grow even more pronounced as the power decreased. "This is a real bottleneck in our development of transistors for low-power applications," he says. "We have to understand the problem before we can fix it—and troublingly, we don't know what's actually happening."

Campbell, who credits NIST colleague K.P. Cheung for first noticing the possibility of trouble with the theory, presented* some of the group's findings at an industry conference on May 19, 2009, in Austin, Texas. Researchers from the University of Maryland College Park and Rutgers University also contributed to the study.


May 24, 2009

Students from Microelectronics Students’ Group win Cadence® Contest

CADENCE® EMEA (Europe, Middle East and Africa regions) organized the first full custom design contest, entitled Virtuoso Olympics. In this unique and innovative event the best layout designers from the top academic institutions in Europe will compete for the title of Fastest full custom layout designer of the year.

Two students from the Microelectronics Students’ Group of the University of Porto (FEUP) won this Cadence® contest. Daniel Oliveira and Américo Dias accepted the challenge and accomplished the target, wining the first place.

May 22, 2009

An interesting discussion in LinkedIn

There is an interesting thread in LinkedIn, started by Antonio Irvin Aquino:

Is there a market for outsourced device modelling/simulation??

By the moment, I've seen no comments, but I should think that, at least, there is a market for outsourced device models courses...

May 18, 2009

IEDM'09


The 2009 IEEE International Electron Devices Meeting (IEDM) will be held in the Hilton Baltimore Hotel in Baltimore (MD) from December 6 to 9 2009. This time IEDM will not be held in Washington after the San Francisco edition!

IEDM is the top conference in the field of electron devices. It is of course the most competitive one. Only truly outstanding papers are accepted. It is highly recommended that experimental results are shown, also some good simulation papers can be also accepted.

Two short courses will be held on Sunday, December 6, on on low power/low energy circuits and scaling challenges.

This year there will also be three plenary presentations. Furthermore, there will be a An Emerging Technology session on "Graphene Nanoelectronics".


Deadline for abstract submissions is June 26 2009 at 5.00 pm Pacific Standard Time.

Topics include all aspects related to electron devices, grouped in several areas:

-CMOS DEVICES & TECHNOLOGY (CDT)
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CHARACTERIZATION, RELIABILITY and YIELD (CRY)
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DISPLAYS, SENSORS, AND MEMS (DSM)
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MEMORY TECHNOLOGY (MT)
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MODELING AND SIMULATION (MS)
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PROCESS TECHNOLOGY (PT)
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QUANTUM, POWER, AND COMPOUND SEMICONDUCTOR DEVICES (QPC)
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SOLID STATE AND NANOELECTRONIC DEVICES (SSN)

This year the area of Modeling and Simulation (MS) explicitly includes "
physical and compact models for devices and interconnects", and also "parameter extraction", and "early compact models for advanced technologies." It seems that compact modeling is considered a more important topic in IEDM than ever before!

If you have important results to show, I vively recommend to send an abstract to IEDM. It is the best place to present them, and to discuss them with the top people. Even if your abstract is rejected, or if you do not have any new results to show, I encourage researchers to attend IEDM, including compact modeling researchers.