An interesting discussion

That is, if someone cares to post... I've get this thread from LinkedIn:

There seem to be a boom in requirement for Device modeling Engineers worldwide from Big Semiconductor Companies as well as small players. Is there a possibility of offshore work in this area too?

You can follow (and post) the discussion here.

Papers on the IEEE Electron Device Letters vol 29 (11), nov 2008

Two interesting papers, I think:

A Variational Approach to the Two-Dimensional Nonlinear Poisson's Equation for the Modeling of Tunneling Transistors

and

Effect of Gate Leakage in the Subthreshold Characteristics of AlGaN/GaN HEMTs

More job offers from linkedIn

I copy the text from LinkedIn:

Looking for R&D Scientist for transistor level (MOSFET, FinFET, etc) research.

- PhD or MSc Microelectronics / Semiconductor Physics or equivalent
- Device Modeling/Simulation (TCAD)
- R&D experience with Universities or Fab/Foundry

Multiple vacancies in East Asia. Email alex at maxima.com.sg for details.

Posted 5 days ago... so hurry up!

As before, we have no relation with this offers, other than passing on the information. For more details, email alex at maxima.com.sg, not us!

Update on the MOS-AK

	1st International MOS-AK Workshop on compact modeling, will be organized in San Francisco (co-located with the CMC Meeting and IEDM Conference) with aims to strengthen a network and discussion forum among experts in the field, create an open platform for information exchange related to compact/Spice modeling, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD tool vendors. The topics cover all important aspects of compact model development, implementation, deployment and standardization within the main theme - compact models for mainstream CMOS/SOI circuit simulation. The specific workshop goal will be to classify the most important directions for the future development of the compact models and to clearly identify areas that need further research. This workshop is designed for device process engineers (CMOS, SOI, BiCMOS, SiGe) who are interested in device modeling; ICs designers (RF/IF/Analog/Mixed-Signal/SoC) and those starting in that area as well as device characterization, modeling and parameter extraction engineers. The content will be beneficial for anyone who needs to learn what is really behind IC simulation in modern device models. The technical program of MOS-AK Workshop consists of one day of tutorials given by noted academic and industry experts, also a panel session is foreseen. The program will be availabe soon at: http://www.mos-ak.org/sanfrancisco/
Speakers:	Tentative list of the speakers already includes following names (in alphabetic order): Henok Abebe, MOSIS; Gennady Gildenblat, ASU; Hans J. Mattausch, U.Hiroshima; Colin Mcandrew, Freescale; Marek Mierzwinski, Tiburon; Paul Jespers, UC Louvain; Sadayuki Yoshitomi, Toshiba; Xisheng Zhang, Accelicon;
Dates:	2nd announcement - Nov.10 Final workshop program - Dec.1 1st International MOS-AK Workshop - Dec.13 at the Westin St Francis Hotel in San Francisco
Place:	The Westin St. Francis 335 Powell Street, San Francisco California 94102
Registration:	On-Line registration is available
Committee:	Hisayo S. Momose; Toshiba; Session Chair Herve Jaouen, STM; Session Chair Ehrenfried Seebacher, austriamicrosystems; Panel Session Chair Tim K. Smith; Accelicon; Local Arrangement Chair Wladek Grabinski, GMC Suisse; Workshop Manager

Open Ph D Student position in semiconductor device modeling

We offer one scholarship for a Ph D student position in the Department of Electronic Engineering in the Universitat Rovira i Virgili (URV), in Tarragona, Spain.

The duration of the grant will be at least three years, possibly four. The monthly salary will be 1000 Euro/month.

The candidate should have a Bachelor or Master degree in Electrical Engineering, Electronic Engineering, Telecommunication Engineering or Physics. A good background in Semiconductor Physics, Semiconductor Devices, or Integrated Circuit Design will be highly appreciated.

The work to be done by the candidate will be focused on the development of new techniques of characterization and modeling of novel advanced semiconductor devices. It will be related to two European projects in which the hosting group participates.

To get more information about our areas of research in the DEEEA, you can visit the website:

http://sauron.etse.urv.es/DEEEA/angles/recerca/nephos/

Required documents for applicants


Applicants are required to send to the address specified below the following documents (in English or Spanish):

1) a full Curriculum Vitae (as complete as possible)

2) Copy of their diploma

3) copy of their passport

4) Academic certificate including their marks (it is important that the number of hours or credits of each subject appears). It is also very important that the document specifies what is the minimum mark for passing a given subject and what is the maximum mark that can be awarded.

Candidates can send their documents by e-mail, but in fact we will need original and copy documents (or authenticated copy) of them; therefore we also suggest to send the documents by postal mail.

Applications should be sent to:

Prof. Benjamin Iñiguez
Department of Electronic, Electrical and Automatic Control Engineering

Universitat Rovira i Virgili (URV)

Avinguda Països Catalans, 26
43007 Tarragona (Spain)
Email: benjamin.iniguez@urv.cat
Tel: +34977558521 Fax:+34977559610

Deadline: November 8 2008

You can contact Prof. Benjamin Iñiguez (Benjamin.Iniguez@urv.cat) for more information

Tarragona is a medium city (100000 inhabitants) with a Mediterranean climate and many recreation opportunities (nice beaches, theme parks, nature preserves, mountain hiking, touristic resorts and facilities). It is located 100 km Southwest of Barcelona, and it is very well connected by train, bus, highways and even low cost flights from its own airport. Additional information about the University and the department can be found at: www.urv.cat and sauron.etse.urv.es