Article in EDN: Modeling gaps in state-of-the-art mixed-signal SOC design

I've recently found an old (2006) paper on the EDN: Electronics Design, Strategy, News website. (I cannot reproduce it here because of the copyrights).

They discuss a bit about standardization efforts on Compact Modeling, and the different aspects that must be taken into account. I think it is a nice paper, even though it is slightly biased towards BSIM (only a bit: PSP, EKV and HiSIM are also mentioned... but not so extensively....).

Papers in Volume 52, Issue 5, Pages 597-838 (May 2008) of Solid-State Electronics

It seems that this month's harvest has been quite good. There are some quite interesting papers

Low-frequency noise properties of double channel AlGaN/GaN HEMTs
S.K. Jha, C. Surya, K.J. Chen, K.M. Lau and E. Jelencovic

A fully 2-dimensional, quantum mechanical calculation of short-channel and drain induced barrier lowering effects in HEMTs
G. Krokidis, J.P. Xanthakis and N.K. Uzunoglu

Subthreshold characteristics of polysilicon TFTs
Wanling Deng, Xueren Zheng, Rongsheng Chen and Yuan Liu

Physics-based 1/f noise model for MOSFETs with nitrided high-κ gate dielectrics
Tanvir Hasan Morshed, Siva Prasad Devireddy, Zeynep Çelik-Butler, Ajit Shanware, Keith Green, J.J. Chambers, M.R. Visokay and Luigi Colombo

Modeling non-quasi-static effects in channel thermal noise and induced-gate noise in MOS field-effect transistors
Abhay Deshpande and R.P. Jinda

Mobility model for compact device modeling of OTFTs made with different materials
M. Estrada, I. Mejía, A. Cerdeira, J. Pallares, L.F. Marsal and B. Iñiguez

Hot-carrier effects as a function of silicon film thickness in nanometer-scale SOI pMOSFETs
Sung Jun Jang, Dae Hyun Ka, Chong Gun Yu, Won-Ju Cho and Jong Tae Park

Modeling of potentials and threshold voltage for symmetric doped double-gate MOSFETs
A. Cerdeira, O. Moldovan, B. Iñiguez and M. Estrada

MOS-AK

I copy a mail from Wladek Grabinski:

The MOS-AK Eindhoven Workshop's presentations are available on-line
please visit: www.mos-ak.org/eindhoven

I would like to take this opportunity and thank all speakers and presenters for
their valuable contribution to the MOS-AK Meeting at MiPlaza. Selected MOS-AK
publications are recommended for further publications: www.mos-ak.org/eindhoven

Let me also acknowledge the workshop sponsors (MiPlaza, Agilent and Cascade) for
their generous financial support as well as local meeting organizers for their
support, smooth organization and perfect logistic of our modeling event. Such
events are unique platform for continuous promotion of local, European compact
modeling activities.

You are more than welcome to attend and contribute to coming modeling events:
* WCM'08 Workshop June 1-5, 2008, Boston, Massachusetts
* MIXDES'08 June 19-21, 2008 Poznan www.mixdes.org/Special_sessions.htm
* MOS-AK/ESSDERC/ESSCIRC Workshop September 19, 2008 www.mos-ak.org/edinburgh/

An interesting paper

Have a look, and share (if you wish) your comments...

Charge transport in boron-doped nano MOSFETs: Towards single-dopant electronics
Applied Surface Science, In Press, Accepted Manuscript, Available online 12 March 2008
Y. Ono, M.A.H. Khalafalla, K. Nishiguchi, K. Takashina, A. Fujiwara, S. Horiguchi, H. Inokawa and Y. Takahashi

IMEC reports methodology to analyze process variability compatible with DFM tools

It seems that, looking through the inherent self-publicity, the report (presented in DATE'08, by the way) is quite nice. I copy an excerpt here, but you can also access the full report in the original source.

Quoting Rudy Lauwereins, Vice President Nomadic Embedded Systems at IMEC:

"Up to now, most variability characterization work is done internally at IDMs on own technology and IP blocks. However, with the move to fabless and fablite companies, we want to bridge the gap between foundry and fabless companies on design-level impact of using most advanced semiconductor technologies. To this end, we invite IDMs, fabless system companies, fabless digital IP providers and foundries to collaborate within our Technology-Aware Design program to develop the necessary tools for designing reliable systems with variable and unreliable components. IMEC’s program is compatible with confidentiality constraints for high value proprietary IP blocks."