Primer Seminario en Nanoelectrónica y Diseño Avanzado 2007

A friend of mine (Francisco J. Garcia Sanchez) has sent me the announcement of the first Seminar on Nanoelectronics and Advanced Design to be held at the INAOE in Puebla, Mexico. Here you have the link: http://www-elec.inaoep.mx/castour2007

The program is VERY interesting, with five stellar speakers, and, best of all, the admision is free...

P R O G R A M

Dr. Francisco J. Garcia Sanchez, /Universidad Simón Bolivar, Caracas, Venezuela
De la Microelectrónica a la Nanoelectrónica: Una Visión de la Evolución de los Dispositivos Electrónicos.

Prof. Krishnendu Chakrabarty, /Duke University, USA
Modular Testing of Core-Based System-on-Chip Integrated Circuits.

Prof. Rajendra Singh, /Clemson University, South Carolina, USA
Nanotechnology and Pathways to Green Energy Conversion

Prof. Naveen K. Yanduru , /Design Manager, Texas Instruments, Inc. Dallas, Tx, USA
Front-ends in deep sub-micron CMOS with an example of a WCDMA, GSM/GPRS/EDGE receiver front-end without inter-stage SAW filter in 90nm CMOS.

Dr. Mauricio Terrones, /Advanced Materials Department, IPICyT, San Luis Potosí, México.
Recent Advances on N-doped Carbon Nanotubes: Applications and Biocompatibility

For more information:
Dr. J. Alejandro Díaz
ajdiaz@inaoep.mx
Tel y Fax: (222) 2470517

Agilent Announces New HVMOS Package For IC-CAP Software

I copy part of the press release (please note the language they use):

Agilent Technologies Inc. announced the availability of a new parameter extraction solution for high voltage (HV) complementary metal oxide semiconductor (CMOS) devices used in a range of automotive and consumer products, as well as LCD and display driver applications. The HVMOS extraction package, for use with Agilent's Integrated Circuit Characterization and Analysis Program (IC-CAP) software platform, enables engineers to model HV CMOS devices using Synopsys' HSPICE simulator, HVMOS Level 66 compact model.

Implemented as a compact model in HSPICE, HVMOS Level 66 compact model outperforms most other HVMOS model solutions in speed and convergence. The HVMOS model includes all relevant physical effects unique to high-voltage operation, including symmetric and asymmetric source and drain resistances, quasi-saturation, transconductance fall off at high-gate voltage, and self-heating effects. As a result, it allows HV CMOS devices to be modeled with unparalleled DC and capacitance modeling accuracy and simulation speed. HVMOS models are used by both analog and digital designers during circuit simulation.

Source: Semiconductor Online

Statistical simulation of memories

In the last issue of electronics letters (August 2 2007, vol 43, issue 16), there is an interesting paper on statistical simulation of sub-100nm memories. Here you have the link to the abstract, and try to have a look at it. I think that this (I mean: incorporating statistical techniques into the whole model) is an issue for a good compact model to be accepted by the design community.
Otherwise, if there is no way to take into account the huge variations in modern technologies, the model will be quite useless for them.

Scaling effects on short-channel organic transistors

If you are interested in organic transistors, perhaps you will appreciate having a look at the paper "Scaling effect on the operation stability of short-channel organic single-crystal transistors", appeared in the Applied Physics Letters of 6 August 2007 (link).
As they say in the abstract: "Organic single-crystal transistors allowed the authors to investigate the essential features of short-channel devices. Rubrene single-crystal transistors with channel lengths of 500 and 100 nm exhibited good field-effect characteristics under extremely low operation voltages, although space charge limited current degrades the subthreshold properties of 100 nm devices. Furthermore, bias-stress measurements revealed the remarkable stability of organic single-crystal transistors regardless of device size. The bias-stress effect was explained by the trapping of gate-induced charges into localized density of states in the single-crystal channel."

ISCAS'08

The 2008 IEEE International Symposium of Circuits and Systems (ISCAS 2008) will be held in Seattle (Washington, USA), on 18-21 May 2008.

ISCAS is the largest conference in the area of Circuits and Systems. It is sponsored by the IEEE Circuits and Systems Society. Prestigeous speakers in this field are always invited.

ISCAS 2008 will focus on the theme "Green Circuits and Systems: Engineering the Environmental Revolution".

The deadline for regular paper submission is October 5 2007. As indicated in the Call for Papers, the scope of ISCAS 2008 includes all topics related to integrated circuits and systems. Papers on compact modeling for circuit design are considered to address some of the topic of the call. In fact, every year a number of interesting papers on compact modeling are presented at ISCAS.

It is important to mention that in ISCAS posters are very well considered, as important as oral presentations. Many authors choose poster as their presentation format.

On the other hand, a "rich and intersting social programme is planned". It still has to be announced. Sounds promising, anyway.