Compact charge and capacitance models of nanowire MOSFETs

The compact modeling of nanowire MOSFETs (also called surrounding gate MOSFETs or Gate All Around MOSFETs) is a hot topic. The first compact drain current models were published in 2004:

Researchers are now addressing the compact modeling of charges and capacitances. In January 2007, in IEEE Transactions on Electron Devices, the first compact model for charges and capacitances of surrounding gate MOSFETs was published: Analytical Charge and Capacitance Models of Undoped Cylindrical Surrounding-Gate MOSFETs, by Moldovan O., Jiménez D., Roig J. and Iñiguez B.


In March 2007, a new charge model for surrounding gate MOSFETs has been published in IEEE Transactions on Electron Devices: Analytic Charge Model for Surrounding-Gate MOSFETs, by Yu B., Lu W.-Y., Lu H. and Taur, Y.


Both models are based on the electrostatic potential soultion obtained by D. Jimenez et al. (Continuous analytic I-V model for surrounding-gate MOSFETs, IEEE Electron Device Letters, August 2005)
from the 1-D Poisson's equation in the radial direction (neglecting the effect of the lateral field). B. yu et al use the initial formulation proposed by Jimenez; charge and capacitances are written in terms of a variable which depends on the surface potential, and is calculated iteratively at the source and drain ends of the channel. Moldovan uses a charge-based formulation: from a charge control model, developed by B. Iñiguez et al. (Explicit continuous model for long-channel undoped surrounding gate MOSFETs, IEEE Transactions on Electron Devices, August 2005)
from the analysis of D. Jimenez et al, analytical expressions of charges and capacitances are obtained in terms of the mobile charge sheet densities at the source and drain ends of the channel; explicit expressions of the mobile charge sheet denisities are finally used.

Special Compact Modeling Session in the MIXDES'07 Conference

Dr Wladek Grabinski, chair of the MOS-AK Group (MOS Modeling and Parameter Extraction Working Group), is organizing, as in the last years, a Special Compact Modeling Session in the frame of the 14^th International Conference Mixed Design of Integrated Circuits and Systems (MIXDES'07).

MIXDES'07 is held in the beautiful town of Ciechocinek (a renowned spa in Poland), 21-23 June 2007. The deadline for regular paper submission is March 12 2007. Prospective authors for the Special Compact Modeling Session should contact Dr. Wladek Grabinski.

MIXDES has become one of the most important microelectronics conferences in Central Europe. Every year an important number of very relevant contributions from all around the world (of course, the majority from Europe) are presented at MIXDES. Prestigeous researchers are invited to give talks for the plenary session and also for the special sessions.

This year, one of the invited presentations, given by myself, will be devoted to the TFT Compact Modeling. It is entitled: "Modeling of Thin Film Transistors for Circuit Simulation"

The Special Compact Modeling Session, held every year under the umbrella of MIXDES, has become a very interesting forum for the discussion and the exchange of information regarding compact modeling issues.

I recommend compact modeling researchers to participate in the MIXDES Special Compact Modeling Session. Contributions are always of very high quality. And I wish to mention that MIXDES has always a superb social programme.

Threshold voltage models

As each month, I've been performing a review of some of the more interesting literature. Today, I'll point out three papers, all of them in the current issue of IEEE Trans. El. Devices, and all three of them dedicated to threshold voltage modeling.
The first one is Threshold-Voltage Modeling of Body-Tied FinFETs (Bulk FinFETs), by Choi, B.-K. Han, K.-R. Kim, Y. M. Park, Y. J. Lee, J.-H. Someday I shall comment something about threshold voltage extraction methods, because it is quite interesting. However, this will not be today.
The second paper is Compact Analytical Threshold-Voltage Model of Nanoscale Fully Depleted Strained-Si on Silicon–Germanium-on-Insulator (SGOI) MOSFETs by Venkataraman, V.; Nawal, S.; Kumar, M. J. I think that the title is quite self-explanatory.
Finally, the third one is Analytical Model of the Threshold Voltage and Subthreshold Swing of Undoped Cylindrical Gate-All-Around-Based MOSFETs, by some friends: Hamdy El Hamid; Iniguez, B.; Roig Guitart, J.
There is a point I'd like to make: all of them are dedicated to different devices, using different technologies. This is a demostration that Iroshi Iwai is right when he says that we've got work for still some fourty or fifty years more, and that it will be possible to evade the classic Moore's Law (perhaps it should be called Moore's Guideline).

ESSDERC'07

The 2007 European Solid-State Device Research Conference (ESSDERC) and European Solid-State Circuits Conference (ESSCIRC) will be held in Munich from 11 - 13 September 2007 (about one week before Oktoberfest).

As you may know, ESSDERC is the most prestigeous European conference on electron devices. The acceptance rate is usually less than 50%.

The deadline for paper submissions is April 7 2007.

This year compact modeling appears explicitly as one of the themes for papers to be submitted to ESSDERC:

"Compact, numerical, and physical modeling; device simulation; behavior models; quantum mechanical and non-stationary transport phenomena; ballistic transport; scattering models; process dispersions, parameter fluctuations, variability; TCAD; mixed electrical-thermal modeling and simulation."

Furthermore, on September 14 2007, one day after the end of ESSDERC and ESSCIRC, the MOS-AK Workshop on Compact Modeling will take place.

A friend of mine (Oana Moldovan) has sent me a very interesting website: the NanoHUB. As they say: " The nanoHUB, a web-based resource for research, education, and collaboration in nanotechnology, is an initiative of the NSF-funded Network for Computational Nanotechnology (NCN). The NCN is a network of universities with a vision to pioneer the development of nanotechnology from science to manufacturing through innovative theory, exploratory simulation, and novel cyberinfrastructure. NCN students, staff, and faculty are developing the nanoHUB science gateway while making use of it in their own research and education. Collaborators and partners across the world have joined the NCN in this effort."

Great for you! My congratulations for a so nice site!