Oct 16, 2019

Top Ten (+2) Companies For US Patents https://t.co/oeNFCdXZTj #paper https://t.co/SdScSwJB3c


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October 16, 2019 at 10:23AM
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Oct 15, 2019

#Space #Radiation and Its Effects on #Electronic Systems https://t.co/MK7pzndDFL #paper https://t.co/p6BseiZGES


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October 15, 2019 at 08:38PM
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Your #Future #RaspberryPiCPU Could Be Made From #Bacteria https://t.co/ABMbYvshSF #paper https://t.co/eloydfpGD9


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October 15, 2019 at 08:33PM
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#TSMC to present 5nm CMOS, 22nm STT-MRAM at #IEDM https://t.co/alFyUIzWqK #paper https://t.co/ju4zRE0oyX


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October 15, 2019 at 06:42PM
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[#paper] S.M. Mohd Hassan, A. Marzuki; Millimeter-wave CMOS Transistor Design and Modelling: A Review; IJSAR , 6(10), 2019; 01-14 https://t.co/yz0cTjl3DM https://t.co/QHDk8m7luW


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October 15, 2019 at 09:04AM
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Oct 14, 2019

#OpenSource Hardware Trends, #Arm Takes a Different Tack https://t.co/ATXoMCU2qI https://t.co/uxhMZlgmRM


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October 14, 2019 at 04:03PM
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#OpenHardware #CfP #OpenSource Computer Aided Design #CAD and Modeling devroom at FOSDEM 2020 https://t.co/woFwcGzemc https://t.co/auoGQMk45L


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[Open Hardware] [CfP] Open Source Computer Aided Design and Modeling devroom at FOSDEM 2020

We are pleased to announce the CfP for

Open Source Computer Aided Design and Modeling devroom 
at FOSDEM 2020
1-2 February 2020, Brussel, Belgium.

The devroom will take place on Saturday, 1 February 2020, at [ULB (Campus Solbosch)](https://www.openstreetmap.org/node/1632534522), in Brussels, Belgium.

We hope you'll join us for a full day of talks, demos and interesting discussions on designing, modeling and testing hardware using Open Source tools. We welcome any talk proposals about the creation of physical objects. Topics of interest include, but are not limited to:

- Circuit Design
    * Printed circuit board design tools
    * Circuit simulation
- 3d modeling and analysis
    * Solid modeling tools
    * Meshing, modeling and transforming physical representations
    * Finite element analysis
- 3d printing
    * 3d slicing tools
    * Motor control
- Machine design and integration
    * Open Hardware projects
    * ECAD/MCAD integration
    * Thermal analysis
    * Wire modeling
- Physical Model Data storage
    * Data representation and optimization
    * Version control in hardware data storage
    * Collaborative and team-based hardware design techniques

Slots will be allocated for short (20 minutes) and long (40 minutes) talks. Speakers need to specify their preferred format. Both include time for questions and answers. Depending on the number of submissions, submitters may be asked to utilize an alternate time format.

The submission process
Please submit your proposals at
https://penta.fosdem.org/submission/FOSDEM20 before 20 November 2019.

If you already have a Pentabarf account (for example as a result of having submitted a proposal in the past), make sure you use it to log in and submit your proposal. Do not create a new account if you already have one.

Please include the following information with your submission:

  • Abstract
  • Preferred Session length
  • Speaker bio
  • Link to any hardware / code /slides for the talk

When you submit your proposal (creating an "Event" in Pentabarf), make sure you choose the "Open Source Computer Aided Design and Modeling" in the track drop-down menu. Otherwise your proposal may go unnoticed. Fill in at least a title and abstract for the proposed talk and a suggested duration. Keep in mind that much of the value in these meetings comes from the discussions, so please allot at least 20% of the talk time for questions and answers.

Important dates
- Call for papers available: 13 October 2019
- Call for participation closes: 20 November 2019
- Devroom schedule available: 15 December 2019
- Devroom day: Saturday 1 February 2020 (09:00 to 17:00)

Recordings
The talks will be recorded and live-streamed during FOSDEM20. The
recordings will be published under the same licence as all FOSDEM
content (CC-BY). Only presentations will be recorded, not informal
discussions and whatever happens during breaks between presentations.
By agreeing to present at FOSDEM, you give permission to be recorded.
Please contact us if you would like to request an exception to the
recording policy for your talk.

Mailing list
Feel free to subscribe to the [Open Source Computer Aided Design and
Modeling mailing list](https://lists.fosdem.org/listinfo/open-hardware-devroom)
to submit ideas, ask questions and generally discuss about the event.
_______________________________________________
open-hardware-devroom mailing list
open-hardware-devroom@lists.fosdem.org
https://lists.fosdem.org/listinfo/open-hardware-devroom
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Oct 11, 2019

#GaN as a key material for establishing a #sustainable society by Hiroshi Amano is a Japanese physicist, engineer, and inventor, awarded the 2014 #Nobel Prize in Physics 14 October 2019 | 12:15pm-1pm | EPFL Forum Rolex https://t.co/ti6j4BvrCW #paper https://t.co/XBoGbSAeps


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October 11, 2019 at 08:39PM
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Oct 10, 2019

article with 700 reads

Wladek Grabinski, Matt Bucher,Jean-Michel Sallese and François Krummenacher
Journal of Telecommunications and Information Technology (3-4):31-42, March 2000



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Mukku P.K., et al. (2020) Recent Trends and Challenges on Low-Power FinFET Devices. In: Smart Intelligent Computing and Applications. Smart Innovation, Systems and Technologies, vol 160. https://t.co/Nzgcx7NKME #paper https://t.co/OEqyhNfDKC


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October 10, 2019 at 11:21AM
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#UNICEF Launches #Cryptocurrency Fund to Back #OpenSource Technology https://t.co/bLVBN5LLVt https://t.co/EZTMhieghQ


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October 09, 2019 at 11:32PM
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A modular point contact spectroscopy probe for sub-Kelvin applications https://t.co/9FqoTXIFaL #paper https://t.co/a8wRm5LpHB


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October 09, 2019 at 11:46PM
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Oct 8, 2019

Today Is Ada Lovelace Day 2019 #ALD19 @findingada https://t.co/qdbQcH2MN3 #paper https://t.co/JlUXrMUbJh


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October 08, 2019 at 11:49AM
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Oct 7, 2019

#IHP #XFAB- #SiGe:C #BiCMOS technologies https://t.co/pcpzyGg2iA #paper https://t.co/VKdztp0I39


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October 07, 2019 at 06:37PM
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2019 IEDM Tutorials with: Cryogenic MOSFET Modeling, Christian Enz, EPFL (Dec.7 4:30 pm – 6:00 pm)https://t.co/RGJd5Wabyc #paper https://t.co/LypIMWA8bC


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October 07, 2019 at 06:36PM
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The 31st IEEE ICM 2019 C4P The IEEE ICM has been held in numerous countries across the Middle East, Southern Europe, and Asia for the past 30 years. The conference will take place in the city of the world-famous Egyptian Pyramids https://t.co/94kixyF0uE #paper https://t.co/FbrChTqMoA


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October 07, 2019 at 06:36PM
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T. A. Oproglidis et al., "Upgrade of Drain Current Compact Model for Nanoscale Triple-Gate Junctionless Transistors to Continuous and Symmetric," in IEEE TED, vol. 66, no. 10, pp. 4486-4489, Oct. 2019. https://t.co/RzBjfLbzpY #paper https://t.co/Rr0RT9NF03


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Oct 3, 2019

IEEE EDS Distinguished Lecturer by ED Poland Chapter

IEEE EDS Distinguished Lecturer by ED Poland Chapter
Krzysztof Górecki and Daniel Tomaszewski

EDS Distinguished Lecturer, Professor Mansun Chan (UST, Hong Kong) gave a talk titled “Simulation and Modeling of Dynamic Systems with Time Varying Device Characteristic” on May 21, 2019, at Łukasiewicz Research Network—Institute of Electron Technology (Łukasiewicz ITE), Warsaw, Poland. Approximately 15 persons from ITE and from abroad, traveled to Warsaw for the ESSDERC paper selection meeting and to attend the lecture.

The abstract of the Distinguished Lecture: The existing circuit simulation methodologies are based on time-invariant device models, electrical characteristics and parameters of which do not change over time. However, more recently, many new applications such as neuromorphic computing or artificial neural-network circuits require the use of devices with history dependent behavior. Due to such a behavior different from traditional transistors, which are the focus for the compact modeling community, a new approach to monitor the time dependent characteristics of these devices is necessary. In addition, a new simulation methodology is also required to predict the behavior of such system efficiently. In the presentation, a new approach to simulate dynamic systems was introduced. The proposed approach combined with the modification of simulation flow and compact model construction was introduced. The approach is very general and can be used to cover a wide class of devices with dynamic behavior such as memory function or device performance degradation during a prolonged operation.

A Mini-Colloquium was organized by the ED Poland Chapter in cooperation with: Gdynia Maritime University, Gdynia, Poland, Łukasiewicz Research Network—Instytut Technologii Elektronowej (Łukasiewicz-ITE), Warsaw, Poland, and a Department of Microelectronics and Computer Science, Lodz University of Technology, Lodz, Poland. Approximately 20 persons attended the full-day event. Nine interesting talks were presented by internationally recognized experts in the area of nanoelectronics, including three EDS Distinguished Lecturers (DLs).

Prof. Shinichi Takagi (The University of Tokyo) presented a talk “Tunneling FET technology for ultra-low power logic applications” addressing critical issues, technical challenges and viable technologies of TFETs using a variety of semiconductors such as Si, Ge and oxide semiconductors. Device engineering indispensable in improving the performance of TFETs were summarized with emphasis on the source junction formation technology and the optimal material design. The electrical characteristics of TFETs using Si and Ge homo junctions, Ge/strained SOI hetero-junctions and ZnO/(Si, Ge) hetero-junctions were presented as the viable examples.

Prof. Andrzej Strójwąs (PDF Solutions, and Carnegie Mellon University) had a talk “New Product Introduction Challenges in the Bleeding Edge Technology Nodes,” presenting a comprehensive methodology and a full suite of process-design design interaction characterization techniques to enable cost-effective introduction of new products in the 7 nm and below technologies.

Dr. Arkadiusz Malinowski (GlobalFoundries) gave a talk “Will FinFET era last only for 10 years? FinFET scaling challenges for next CMOS technology nodes,” in which challenges related to FinFET metrology/inspection, lithography/overlay, integration/variability, cycle time and cost were addressed.

Dr. Rajiv V. Joshi (DL, IBM Research Division Yorktown Heights) presented a lecture “Variability aware design in nm era.” He highlighted predictive analytical technique based on statistical analysis methodology targeting both memory and custom logic design applications is highlighted. Design case studies both in planar and non-planar technologies were discussed. Finally, the speaker discussed an efficient statistical methodology based on simulation and modeling to evaluate and minimize the aging of memory chips.

Prof. Henryk M. Przewłocki (DL, Łukasiewicz Research Network—ITE Warsaw) presented a talk “Expanding the horizon of photoelectric investigations of the MIS system properties,” in which he discussed an extended theory of the photocurrent vs. gate voltage characteristics, at different wavelengths of light illuminating the structure under test, with diffusion currents taken into account. The theory is in agreement with the relevant experimental characteristics. This opens the possibilities of developing new measurement methods of the MIS system crucial parameters.

Prof. Marcelo Pavanello (DL, Centro Universitario FEI) presented a talk “Performance and modeling of Nanowire-based MOSFETs.” He discussed differences between double-gate, triple-gate and nanowire-based MOSFETs and their characteristics. Also junctionless nanowire transistors (JNTs) were introduced as one of the interesting alternatives for downscaling because of their relative process simplicity compared with inversion-mode nanowires. Different aspects of modeling of the JNT steady-state and dynamic operation was interestingly presented.

Dr. Farzan Jazaeri (EPFL) presented a talk “Cryogenic Electronics and Quantum Computing Architecture.” He made an interesting review of topics of a quantum computation that holds the promise to solve problems that are intractable even for the most powerful supercomputers. Quantum computers process the information stored in quantum bits (qubits). The information in the qubits is fragile, so the qubits must be typically cooled to cryogenic temperature. Spin qubits in silicon were reported that have already been proposed and experimentally demonstrated in academic research laboratories.

Prof. Mike Brinson (London Metropolitan University) presented a talk “Equation-Defined template and synthesis driven compact modelling of semiconductor devices.” He reported current research that links Equation-Defined Device modelling with Verilog-A modules, driven by code templates and synthesis, which in turn result in an improved interactive modelling techniques. Throughout the talk a series of compact device models were introduced to demonstrate the fundamentals and application of the new approach to compact device modelling.

Dr. Władek Grabiński (DL, MOS-AK and GMC) presented a talk “FOSS tools for support of IC modeling and design with special emphasis on Verilog-A standardization.” He discussed selected FOSS CAD tools along complete technology/design tool chain from nanoscaled technology processes. The talk was illustrated by application examples of the FOSS TCAD tools, like Cogenda TCAD and DEVSIM. Compact modeling was related to the parameter extraction and standardization of the experimental and measurement data exchange formats. Finally, present FOSS CAD simulation and design tools: ngspice, Qucs, GnuCap, Xyce were presented.

~ Marcin Janicki, Editor
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[IEEE EDS Update] MIXDES 2019, Rzeszów (PL)

26th International Conference “Mixed Design of Integrated Circuits and Systems"'
MIXDES 2019 
By Marcin Janicki

On June 27–29, 2019, Rzeszów, Poland, the International Conference MIXDES 2019 took place. The event was organized by the Lodz University of Technology together with the Warsaw University of Technology. The conference was co-sponsored by Poland Section IEEE ED & CAS Societies, Polish Academy of Sciences (Section of Microelectronics and Electron Technology), and Commission of Electronics and Photonics of Polish National Committee of International Union of Radio Science—URSI. The 3-day conference program included 97 presentations from 28 countries. The following six general invited talks were presented during the conference plenary sessions:
  • Advanced MOS Device Technology for Low Power Logic LSI Shinichi Takagi (The University of Tokyo, Japan)
  • Quantum Bits and Quantum Computing Architecture Farzan Jazaeri (EPFL, Switzerland)
  • Towards Energy-Autonomous Integrated Systems Through Ultra-low Voltage Analog IC Design Viera Stopjaková (Slovak University of Technology in Bratislava, Slovakia)
  • THz Technologies and Applications Thomas Skotnicki (Institute of High Pressure Physics PAS, Poland)
  • What is Killing Moore’s Law? Challenges in Advanced FinFET Technology Integration Arkadiusz Malinowski (GLOBALFOUNDRIES, USA)
  • Yield and Reliability Challenges at 7nm and Below Andrzej Strojwąs (Carnegie Mellon University, USA)
The sessions also included presentations in the frame of four special sessions:
  • Compact Modeling for Nanoelectronics organized by D. Tomaszewski (Institute of Electron Technology, Poland) and W. Grabiński (GMC, Switzerland)
  • Intelligent Distributed Systems organized by M. Drozd (LTC Sp. z o.o., Poland), R. Sztoch, P. Sztoch (FINN Sp. z o.o., Poland), B. Sakowicz and D. Makowski (Lodz University of Technology, Poland)
  • Large Scale Research Facilities organized by A. Napieralski, W. Cichalewski (Lodz University of Technology, Poland)
  • Thermonuclear Fusion Projects organized by S. Simrock (ITER, France), D. Makowski (Lodz University of Technology, Poland), D. Bocian and M. Scholz (Institute of Nuclear Physics, Poland
The next MIXDES 2020 Conference will take place in Wrocław, Poland. The Preliminary Call for Papers is available at http://www.mixdes.org/downloads/call2020.pdf. More information about the past and next MIXDES Conferences can be found at http://www.mixdes.org.
Edited by Mariusz Orlikowski
MIXDES 2019 Conference Secretary
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[paper] Gallium Nitride FET Model

Gallium Nitride FET Model
V V Orlov, G I Zebrev
National Research Nuclear University MEPHI, Moscow, Russia
E-mail: gizebrev@mephi.ru

Abstract: We have presented an analytical physics-based compact model of GaN power FET, which can accurately describe the I-V characteristics in all operation modes. The model considers the source-drain resistance, different interface trap densities and self-heating effects. (read more 
https://arxiv.org/ftp/arxiv/papers/1909/1909.05702.pdf)

Introduction: Gallium nitride (GaN) high electron mobility transistor (HEMT) technology has many advantages, that make it a promising candidate for high-speed power electronics. It allows high-power operation at much higher frequencies than silicon laterally diffused metal-oxide-semiconductor field-effect transistors (LDMOSFETs), currently a staple for the cellular base station industry [1]. The high breakdown voltage capability (over 100 V), high electron mobility, and high-temperature performance of GaN HEMTs are the main factors for its use in power electronics applications. Circuits design in both application regimes requires the accurate compact device models that can describe the non-linear I-V characteristics. The current state-of-the-art GaN power transistor circuit models are mostly empirical in nature and contain a large number of fitting parameters. The source-drain series resistance and self-heating make the compact modeling difficult [2]. Currently available models are not enough accurate to describe the I-V characteristics of power GaN HEMTs in all operation modes. This means, that we need a compact physics-based analytical model based on the physical description of the device. In this paper, we present a physics-based GaN power transistor model based on generic approach The paper contains 3 parts. In the first part, we will give a concise description of the model. The specific power HEMT’s effects, such as series resistance and self-heating will be discussed in the second and third parts 

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[paper] Prediction of DC-AC Converter Efficiency Degradation

Kenshiro Sato, Dondee Navarro, Shinya Sekizaki, Yoshifumi Zoka, Naoto Yorino,
Hans Jürgen Mattausch, Mitiko Miura-Mattausch, 
Prediction of DC-AC Converter Efficiency Degradation due to Device Aging
Using a Compact MOSFET-Aging Model
IEICE Transactions on Electronics
論文ID 2019ECP5010, [早期公開] 公開日 2019/09/02

Online ISSN 1745-1353, Print ISSN 0916-8524, https://doi.org/10.1587/transele.2019ECP5010,
https://www.jstage.jst.go.jp/article/transele/advpub/0/advpub_2019ECP5010/_article/-char/ja,

Abstract: The degradation of a SiC-MOSFET-based DC-AC converter-circuit efficiency due to aging of the electrically active devices is investigated. The newly developed compact aging model HiSIM_HSiC for high-voltage SiC-MOSFETs is used in the investigation. The model considers explicitly the carrier-trap-density increase in the solution of the Poisson equation. Measured converter characteristics during a 3-phase line-to-ground (3LG) fault is correctly reproduced by the model. It is verified that the MOSFETs experience additional stress due to the high biases occurring during the fault event, which translates to severe MOSFET aging. Simulation results predict a 0.5% reduction of converter efficiency due to a single 70ms-3LG, which is equivalent to a year of operation under normal conditions, where no additional stress is applied. With the developed compact model, prediction of the efficiency degradation of the converter circuit under prolonged stress, for which measurements are difficult to obtain and typically not available, is also feasible.
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Oct 2, 2019

Ph D scholarship about semiconductor device modeling in Tarragona (Spain)

We want to get one scholarship for a Ph D student position in the Department of Electronic Engineering in the Department of Electronic Engineering in the Universitat Rovira i Virgili (URV), in Tarragona , Spain. The subject of the Ph D would be o the development of new techniques of characterization and modeling of nanoscale semiconductor devices, in particular two-dimensional semiconductor devices, (which are one of the most promising device structures for downscaling to 1nm), in particular transistors or memristors. It will be related to funding research projects in which the hosting group participates.

The duration of the grant will be 3 years.

The candidate should have a  Master degree in Electrical Engineering, Electronic Engineering, Telecommunication Engineering or Physics, obtained between January 1 2020 and October  2022. A good background in Semiconductor Physics, Semiconductor Devices, or Integrated Circuit Design will be highly appreciated.

Applicants must send to my e-mail address (benjamin.iniguez@urv.cat), and by November 9 2022, a CV together witha copy of the academic certificates indicating the grades obtained for all subjects during their studies (both Bachelor Degree and Master Degree).

Tarragona is a medium city (100000 inhabitants) with a pleasant Mediterranean climate and many recreation opportunities (nice beaches, theme parks, nature preserves, mountain hiking, touristic resorts and facilities). It is located 100 km Southwest of Barcelona, and it is very well connected by train, bus, highways and even low cost flights from its own airport.

My research group in the Department of Electronic Engineering, Universitat Rovira i Virgili (URV) is one of the strongest groups in compact modeling in Europe. We have led or are leading several national and European projects targeting semiconductor device characterization, physics and modeling.
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Oct 1, 2019

INNOVATORIUM Łukasiewicza https://t.co/Qdpl1oFlpM #paper https://t.co/5kzYx3zoVr


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October 01, 2019 at 03:17PM
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Indium gallium arsenide #InGaAs one-transistor dynamic random access #1TDRAM memory https://t.co/Sog5iidjvf #paper https://t.co/A98MfTkMeI


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October 01, 2019 at 01:52PM
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Sep 30, 2019

#GPU-Powered #SPICE: The Way Forward for #Analog #Simulation https://t.co/rfXIvQ6zS9 #paper https://t.co/M5CoIG3rIt


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September 30, 2019 at 05:14PM
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Sep 3, 2019

The Institute of Nuclear Physics of the Polish Academy of Sciences (IFJ PAN) has developed a model that reveals the nature of crystal defects in silicon carbide (SiC). https://t.co/iY2ZkKIxYG #paper https://t.co/VsWkm0hlxz


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September 03, 2019 at 08:32PM
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Innovative Strategy for Mixer Design Optimization Based on gm/ID Methodology by Giovanni Piccinni, Claudio Talarico, Gianfranco Avitabile and Giuseppe Coviello; Electronics 2019, 8(9), 954; https://t.co/7pjaB0dIt4 https://t.co/1RYwhJfuX9 #paper https://t.co/Y8ftswEgDc


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September 03, 2019 at 04:21PM
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Article reached 1,000 reads

A. Bazigos, M. Bucher, J. Assenmacher, S. Decker, W. Grabinski and Y. Papananos
An Adjusted Constant-Current Method to Determine Saturated and Linear Mode Threshold Voltage of MOSFETs
IEEE Transactions on Electron Devices,
vol. 58, no. 11, pp. 3751-3758, Nov. 2011.
doi: 10.1109/TED.2011.2164080
Abstract:
The constant-current (CC) method uses a current criterion to determine the threshold voltage (VTH) of metal-oxide-semiconductor (MOS) field-effect transistors. We show that using the same current criterion in both saturation and linear modes leads to inconsistent results and incorrect interpretation of effects, such as drain-induced barrier lowering in advanced CMOS halo-implanted devices. The generalized adjusted CC method is based on the theory of the charge-based MOS transistor model. It introduces an adjusted current criterion, depending on VDS , allowing to coherently determine VTH for the entire range of VDS from linear operation to saturation. The method uses commonly available ID versus VG data with focus on moderate inversion. The method is validated with respect to the ideal surface potential model, and its suitability is demonstrated with technology-computer-aided-design data from a 65nm CMOS technology and measured data from a 90nm CMOS technology. Comparison with other widely used threshold voltage extraction methods is provided.
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Sep 2, 2019

G. Darbandy et al., "Characterization of the Charge-Trap Dynamics in Organic Thin-Film Transistors," 26th MIXDES, Rzeszów, Poland, 2019, pp. 76-80. https://t.co/nQs9W9PDJM #paper https://t.co/ROmbZzT1Wi


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September 02, 2019 at 02:45PM
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#IEDM 2019 to Highlight Innovative #Devices for an Era of Connected #Intelligence - Semiwiki https://t.co/TBlZTJtI6g #paper https://t.co/iDwVRos2mw


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September 02, 2019 at 09:40AM
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Aug 30, 2019

G. Hills et al., “Modern microprocessor built from complementary carbon nanotube transistors,” Nature, vol. 572, no. 7771, pp. 595–602, Aug. 2019 https://t.co/pivFGNURgH #paper https://t.co/1FjBr7mNsL


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August 30, 2019 at 11:40AM
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