Sep 27, 2018

System76 To Release A "New #opensource #Computer" https://t.co/CglryyCNZU https://t.co/SN8OYHydYb


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September 27, 2018 at 05:14PM
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[paper] Importance of complete characterization setup on onwafer TRL calibration in sub-THz range

Chandan Yadav, Marina Deng, Magali De Matos, Sebastien Fregonese
and  Thomas Zimmer
IMS Laboratory, University of Bordeaux
351 cours de la Libération – 33405 Talence cedex, France

Abstract: In this paper, we present the effect of different sub-mm and mm-wave probe geometry and topology on the measurement results of dedicated test-structures calibrated with on-wafer TRL. These results are compared against 3D EM simulation of the intrinsic test-structures. To analyze difference between the measured and intrinsic EM simulation results, onwafer TRL calibration performed on EM simulation results of a dedicated test-structure is also presented. 

FIG: 3D view of the Open-M1 where metal-1 (M1) does not have connection with ground as shown in the enlarged view.



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Sep 26, 2018

#Modeling of Electron Devices Based on 2-D Materials. Shortly analyze the main open challenges of modeling 2-D-based electron devices. https://t.co/GkhpFYFS3H


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September 26, 2018 at 02:48PM
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Sep 25, 2018

ST and Leti to make #GaN-on-#Si power #transistors https://t.co/yNCDikxtpE #paper


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September 25, 2018 at 12:15AM
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Sep 22, 2018

Contacting and Gating #2D #Nanomaterials https://t.co/IgqlN6pi1c #paper


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September 22, 2018 at 02:11PM
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Sep 20, 2018

ST's CEO speaks of shame at #European #failure https://t.co/k8TpEYNqkO #paper https://t.co/p5bubkJSXo


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Sep 14, 2018

Ph D student scholarship about compact modeling at URV (Tarragona, Spain)

We offer one scholarship for a Ph D student position in the Department of Electronic Engineering in the Universitat Rovira i Virgili (URV), in Tarragona, Spain.

The duration of the grant will be for three years. The monthly salary will be about 1000 Euro/month, which is more than enough to live in Tarragona. The position will start between January and April 2019.
The candidate should have a Bachelor or Master degree in Electrical Engineering, Electronic Engineering, Telecommunication Engineering or Physics. A good background in Semiconductor Physics, Semiconductor Devices, or Integrated Circuit Design will be highly appreciated.

The work to be done by the candidate will be focused on the development of new techniques of characterization and modeling of novel advanced semiconductor devices, in particular nanoscale MOSFETs under cryogenic conditions for Quantum Computing.This work will be carried out in collaboration with a research team in IMEC in Leuven (Belgium).
The NEPHOS group at URV is one of the most powerful teams in Europe in the area of compact modeling of semiconductor devices.

Required documents for applicants

Applicants are required to send to the address specified below the following documents (in English or Spanish):
1) a full Curriculum Vitae (as complete as possible) with passport number
2) Copy of their diploma
3) copy of their passport
4) Academic certificate including their marks (it is important that the number of hours or credits of each subject appears). It is also very important that the document specifies what is the minimum mark for passing a given subject and what is the maximum mark that can be awarded.
Candidates are requested to send their documents by e-mail to:
Prof. Benjamin IñiguezDepartment of Electronic, Electrical and Automatic Control Engineering
Universitat Rovira i Virgili (URV)
Avinguda Països Catalans, 26
43007 Tarragona (Spain)Email: benjamin.iniguez@gmail.comTel: +34977558521 Fax:+34977559610

Deadline for documents submission: October 6 2018
You can contact Prof. Benjamin Iñiguez (Benjamin.Iniguez@gmail.com) for more information
Tarragona is a medium city (100000 inhabitants) with a Mediterranean climate and many recreation opportunities (nice beaches, theme parks, nature preserves, mountain hiking, touristic resorts and facilities). It is located 100 km Southwest of Barcelona, and it is very well connected by train, bus, highways and even low cost flights from its own airport. Additional information about the University and the department can be found at: www.urv.cat
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Sep 11, 2018

[mos-ak] [press note] MOS-AK Workshop at ESSDERC/ESSCIRC in Dresden, Sept. 3, 2018

16th MOS-AK Workshop at ESSDERC/ESSCIRC
http://www.mos-ak.org/dresden_2018/
Dresden, Sept. 3, 2018

The MOS-AK Compact Modeling Association, a global compact/SPICE modeling and Verilog-A standardization forum, held its 16th MOS-AK Workshop in the timeframe of ESSDERC/ESSCIRC. The event was hosted on September 3rd, 2018, by the TU Dresden in Dresden, Germany. The technical program of the event was coordinated by the MOS-AK TPC Committee. The workshop has received technical program promotion provided by ASCENT Network, Europractice, EPFL EDlab, IJHSES as well as NEEDS of nanoHUB.org

The MOS-AK workshop was opened by Wladek Grabinski, who has welcomed all the attendees. A group of 30+ international academic researchers and modeling engineers attended 10 technical compact modeling presentations covering full development chain from the nanoscaled technologies thru semiconductor devices modeling to advanced IC design support.

The workshop was chaired by Larry Nagel, OEC (USA), Suba Subramaniam, XFAB (D) and Matthias Bucher, TUC (GR). In the first morning session Wladek Grabinski gave an overview of the MOS-AK Community. Afterwards, Prof. Muhammad Mustafa Hussain from KAUST (SA) held a talk of "Physically Compliant CMOS Electronics Enabled Interactive Electronic System". It followed a talk by Dr. Sadayuki Yoshitomi from Toshiba Memory Corp. (J) gave some insights of "RF CMOS Compact modeling technologies past and future".
Krishna Pradeep from ST Microelectronics (D) started the second morning session with a talk entitled "Analysis and modeling of wafer level process variability in advanced FD-SOI devices using split C-V and gate current data". Kerim Yilmaz from TH Mittelhessen (D) offered a modeling approach for "Scaling correlation between DG & GAA MOSFETs". Dr. Laurie Calvet from University Paris-Sud (F) held a talk on "Compact Modeling for Neuromorphic Applications". The morning session ended with "Advanced PDK and Technologies accessible through ASCENT" by Dr. Luca Perniola from CEA (F).

The afternoon session continued with four additional talks, where Dr. Farzan Jazaeri from EPFL (CH) gave a talk on "Reliability Modeling in Harsh Radiation for Space Applications". Prof. Benjamin Iniguez from URV (SP) explained the latest results on "Low frequency noise modeling of organic and IGZO TFTs". Dr. Mike Schwarz from NanoP (D) continued with the topic "Schottky Barrier MOSFET Device Physics for Cryogenic Applications". The session was closed by a talk of Dr. Daniel Tomaszewski, ITE (PL), on various methodologies of "Compact Modeling for Process and Device Characterization".

The MOS-AK speakers have shared their latest perspectives on compact/SPICE modeling and Verilog-A standardization in the dynamically evolving semiconductor industry and academic R&D. The event featured advanced technical presentations covering compact model development, implementation, deployment and all the presentations are available online for download at http://www.mos-ak.org/dresden_2018/.


Photo: Part of the participants of the 16th MOS-AK Workshop at ESSDERC/ESSCIRC

Afterward all the participants could follow ESSDERC Track4 "Compact modeling of devices and circuit" on Sept. 5-6, 2018
Wednesday 14:20-15:40 B4L-G Compact Modeling (3 papers)
Chair: Wladek Grabinski, Thierry Poiroux
Thursday 10:20-12:0 C2L-F Compact Modeling of Electron Devices (4 papers)
Chair: Daniel Tomaszewski, Benjamin Iniguez

The MOS-AK Association plans to continue its standardization efforts by organizing future compact modeling meetings, workshops and courses in Europe, USA, China and India throughout coming 2018/2019 years, including:
About MOS-AK Association:
MOS-AK, an international compact modeling association primarily focused in Europe, to enable international compact modeling R&D exchange in the North/Latin Americas, EMEA and Asia/Pacific Regions. The MOS-AK Modeling Working Group plays a central role in developing a common information exchange system among foundries, CAD vendors, IC designers and model developers by contributing and promoting different elements of compact/SPICE modeling and its Verilog-A standardization and related CAD/EDA tools including FOSS for the compact/SPICE models development, validation/implementation and distribution. For more information please visit: mos-ak.org

   
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Sep 10, 2018

Jushan Xie New Vice-Chair of #Si2 #Compact #Model Coalition #CMC https://t.co/5P0iKUCOD3 https://t.co/L8Yv0gq1m3


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September 10, 2018 at 06:34PM
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18 #Python programming books for beginners and veterans https://t.co/DbR7XiA3Sr #opensource


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September 10, 2018 at 09:34AM
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Sep 8, 2018

Design of an ultralow power CNTFET based 9T SRAM with shared BL and half select free techniques #paper IJNM https://t.co/pltPaaF9SI


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September 08, 2018 at 04:32PM
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#FOSSCON 2018: Where #OpenSource and #LEGO Collide | Tux Machines https://t.co/SfKMUbpYVq


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September 08, 2018 at 01:09PM
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Sep 6, 2018

Ultrahigh-Sensitive #CMOS pH #Sensor Developed in the BEOL of Standard 28 nm #UTBB #FDSOI https://t.co/Mdbk2AswjV #paper


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September 06, 2018 at 06:29PM
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#SPICE #Modeling of #Photoelectric Effects in Silicon With Generalized Devices - IEEE Journals & Magazine https://t.co/QecgTxVHhR


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September 06, 2018 at 02:46PM
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Aug 28, 2018

Fujitsu triples output #power of #GaN #HEMTs https://t.co/mx7SeL9xSD #paper


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Aug 23, 2018

C4P: Reliability of CMOS Logic, Memory, Power and Beyond CMOS Devices

Call for Papers for a Special Issue 
of IEEE Transactions on Electron Devices
on “Reliability of CMOS Logic, Memory, Power and Beyond CMOS Devices”

Submission deadline: March 31, 2019; Publication date: October 2019

Reliability of electronic devices continues to remain as a serious issue for several technology generations. Bias Temperature Instability (BTI) continues to impact CMOS logic devices for High-K Metal Gate (HKMG) technologies, while Hot Carrier Degradation (HCD) and Self Heating Effect (SHE) have evolved as additional issues for FinFETs. The Time Dependent Dielectric Breakdown (TDDB) is still a concern and needs attention. These topics are also of interest for future devices with different channel materials (such as SiGe, Ge or III-V) and architectures (such as Gate All Around Nano Sheet FETs). The mechanisms governing degradation of program/erase window with cycling, data retention before and after cycling, etc. in conventional Vertical NAND and different emerging memories such as Resistive RAM, Phase Change RAM, Magnetic RAM and Ferroelectric RAM are of interest. Different power devices (Si and SiC FETs, IGBTs, GaN HEMTs) are becoming mainstream now and their reliability needs to be accessed. Finally, very little has been studied on the reliability of futuristic 2D channel devices.

This Special Issue of the IEEE Transactions on Electron Devices will feature the most recent developments and the state of the an in the field of device reliability based on both experimental results and theoretical models. Papers must be new and present original material that has not been copyrighted, published or accepted for publications in any other archival publications, that is not currently being considered for publications elsewhere, and that will not be submitted elsewhere while under considerations by the Transactions on Electron Devices.

Topics of interest include, but are not limited to:

  • Advanced Transistors: Negative and Positive Bias Temperature Instabilities; Hot Carrier Degradation; SelfHeating Effects; De-convolution of BTI-HCI-SHE; Variability; Random Telegraph Noise; Alternative (SiGe, Ge and III-V) channels; Novel device architectures; etc.;
  • Gate Dielectrics: Charge trapping and breakdown including TDDB; Reliability of novel gate dielectrics and materials for logic and memory devices; Evaluation and modeling of progressive breakdown; Gate dielectric reliability on SiGe, Ge and III-V channels; etc.;
  • Reliability of Memory Devices: DRAM and NVM including 2D and 3D NAND; Novel memory devices such as Re-RAM, Phase Change RAM, MRAM; etc.;
  • Power Devices: MOSFET, HEMT, IGBT on different materials (GaN, SiC, Ga203); etc.;
  • RF Devices: High frequency effects; GaN HEMT; RF 801 etc.
  • Novel Devices: Negative Capacitance FETs; Ferroelectric memory FETs; Tunnel FETs; Transistors with 2D semiconductors (graphene, M082); Spintronic devices; Neuromorphic devices, etc.;
  • Process-Related Reliability: Reliability issues related to different fabrication processes and layout for the above devices.
  • Device-Circuit Correlation: Impact of device reliability on circuit operation including any correlation between different effects; development of compact models; circuit simulation; etc.

Submission instructions: Manuscripts should be submitted in a double column format using an IEEE style file. Please visit the following link to download the templates:
http://www.ieee.org/publications_standards/pub1ications/authors/author_templates.html

In your cover letter, please indicate that your submission is for this special issue.

Submission deadline: March 31, 2019 Publication date: October 2019

Guest Editors:

  1. Dr. Andreas Kerber, Globalfoundries, USA
  2. Dr. Chandra Mouli, Micron Technology Inc., USA
  3. Prof. Durga Misra, New Jersey Institute of Technology, USA
  4. Prof. Gaudenzio Meneghesso, University of Padova, USA
  5. Dr. James Stathis, IBM, USA
  6. Prof. Ninoslav D. Stojadinovié, University of Nis, RS
  7. Dr. Randy Koval, Intel, SG
  8. Prof. Souvik Mahapatra, Indian Institute of Technology, Bombay, IN (Guest EIC)
  9. Dr. Stephen Ramey, Intel, USA
  10. Prof Tibor Grasser, TU, Wien, A


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Aug 22, 2018

FOSDEM 2019 Call for Participation

XIX FOSDEM Edition 
Saturday 2nd and Sunday 3rd February 2019 
ULB Campus Solbosch in Brussels.

We now invite proposals for main track presentations, developer rooms, stands and lightning talks. FOSDEM offers open source and free software developers a place to meet, share ideas and collaborate. Renowned for being highly developer oriented, the event brings together some 8000+ geeks from all over the world. We will record and stream all main tracks, devrooms and lightning talks live. The recordings will be published under the same license as all FOSDEM content (CC-BY). If, exceptionally, you believe there is a legitimate reason why your presentation should not be streamed or recorded, you must seek our agreement before submitting it.

Main Tracks
Previous editions have featured main tracks centered around security, operating system development, community building, and many other topics. Presentations are expected to be 50 minutes long (including audience questions) and should cater to a varied technical audience. The conference covers reasonable travel expenses agreed in advance and arranges accommodation for accepted main track speakers if needed.

Proposals for main track presentations should be submitted using Pentabarf: https://fosdem.org/submit. If you already created an account in the system for a previous edition, please reuse it rather than re- registering.

Submissions will be reviewed in two batches, beginning with those received by 13 October. The final deadline is 3 November.

Questions or remarks? Contact us at program@fosdem.org.

Key dates:
13 October: deadline for first batch of main track proposals
3 November: final deadline for main track proposals
1 November onwards: main track talks announced (in batches)

Developer Rooms
Developer rooms are assigned to self-organising groups to work together on open source and free software projects, to discuss topics relevant to a broader subset of the community, etc. Most content should take the form of presentations. Proposals involving collaboration across project or domain boundaries are strongly encouraged.

Developer room proposals should be submitted through the form at
https://fosdem.org/devroom which contains further information.

Questions or remarks? Contact us at devrooms@fosdem.org.

Key dates:
20 September: deadline for developer room proposals
30 September: accepted developer rooms announced
16 October (or earlier): developer rooms issue Calls for Participation
15 December (or earlier): developer rooms publish complete schedules

Stands
FOSDEM offers open source and free software projects the opportunity to display their work during the event. At its stand, a project can share information, demo software, sell merchandise, give away goodies, and so on, and personally interact with the visitors.

What we offer:
- one 180x80cm table, positioned in one of the buildings with developer
  rooms, for the entire duration of the conference. A second table is
  possible in a few cases, but the pressure on space means this is
  becoming increasingly rare and needs strong justification. Joint
  submissions that share a table between related projects will be
  favoured in the selection process.
- two chairs per table
- one power socket type C/E (if you require adapters or additional
  sockets, please bring them yourself)
- fast uplink shared wireless Internet access

To apply, please fill out the form at: https://fosdem.org/stands which
contains further information.

Questions or remarks? Contact us at stands@fosdem.org.

Key dates:
2 November: deadline for stand proposals
11 November: accepted stands announced

Lightning talks
Lighting talks are short — 15 minute long — talks on a wide variety of topics. Anyone who has something interesting to say about an open source or free software topic can apply. We particularly encourage topics that do not fit in any of the developer rooms.

Proposals for lightning talks should be submitted using Pentabarf: https://fosdem.org/submit. Please select "lightning Talks" in the "track" field. If you already created an account in the system for a previous edition, please reuse it rather than re-registering.

Questions or remarks? Contact us at lightningtalks@fosdem.org.

Key dates:
24 November: deadline for lightning talk proposals
15 December: accepted lightning talks announced

All deadlines are at 23.59 UTC.
_______________________________________________
FOSDEM mailing list
FOSDEM@lists.fosdem.org
https://lists.fosdem.org/listinfo/fosdem
_______________________________________________
open-hardware-devroom mailing list
open-hardware-devroom@lists.fosdem.org
https://lists.fosdem.org/listinfo/open-hardware-devroom
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Aug 21, 2018

Cryogenic MOS Transistor Model https://t.co/yuB4LVzdrZ #paper This paper presents a physics-based analytical model for the MOST operating continuously from room temperature down to 4.2K from depletion to strong inversion and in the linear and saturation regimes.


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August 21, 2018 at 01:48PM
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A Review of #Silicon #Photonics https://t.co/NW3NKTiUXq #paper


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August 20, 2018 at 10:43PM
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Aug 18, 2018

Bluespec, Inc. Releases a New Family of #OpenSource #RISC-V #Processors https://t.co/qtfdmtXjqe


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August 18, 2018 at 03:23PM
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Special issue on advanced solution methods for #modeling complex electromagnetic problems - Wang - - International Journal of Numerical Modelling: Electronic Networks, Devices and Fields - Wiley Online Library https://t.co/FbeN2V72B7


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August 18, 2018 at 12:14PM
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Aug 15, 2018

64th #IEDM takes shape https://t.co/kZO0k6jQT3 #paper https://t.co/EvN7mrTRuH


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August 15, 2018 at 09:16AM
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#Purdue re-designs #FETs https://t.co/MOPlUdXlQx #paper https://t.co/8C4ZwWL0vG


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August 15, 2018 at 09:12AM
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Aug 13, 2018

Accurate semi empirical predictive #model for doped and undoped double gate #DG #MOSFET (Solid-State Electronics Available online 4 August 2018) https://t.co/klJRI2hywk https://t.co/Y3PoUrYO58


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August 13, 2018 at 10:02AM
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Aug 11, 2018

#FOSDEM 2019 - Call for participation #C4P https://t.co/t7BFGjDvy5 #paper


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August 11, 2018 at 03:35PM
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Aug 10, 2018

Physical Insights on #Quantum Confinement and Carrier Mobility in Si, Si0.45Ge0.55, Ge Gate-All-Around #NSFET for #5nm Technology Node - IEEE Journals & Magazine https://t.co/EVcK4twqtW #paper


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August 10, 2018 at 01:32PM
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Why Join an #OpenSource Software #Foundation? - SourceForge Community Blog https://t.co/r9AyUXGnwc


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Aug 8, 2018

Hybrid Systems-in-Foil: Enabler or Flexible Electronics

Presented by: Joachim N. Burghartz
Date: 22 August 2018
Time: 11 AM – 12 PM EDT 

Hybrid Systems-in-Foil: Enabler or Flexible Electronics - Flexible electronics add mechanical flexibility, shape adaptivity and stretchability as well as large-area place ability to electronic systems, thus allowing for conquering fundamentally new markets in consumer and commercial applications. Hybrid assembly of large-area devices and ultra-thin silicon chips on flexible substrates is viewed as an enabler to high-performance and reliable industrial solutions as well as to high-end consumer applications of flexible electronics. This talk discusses issues in ultra-thin chip fabrication, device modeling and circuit design, as well as assembly and interconnects for thin chips embedded into foil substrates in which flexible large-area components are implemented for an overall optimized Hybrid System-in-Foil (HySiF).

This message is being sent to you on behalf of Tian-Ling Ren, EDS Education Committee Chair. All participants will receive WebEx details prior to the event. We sincerely hope that you can join us for these special events. Register Now!
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#Nanostructured gate dielectric boosts stability of #organic thin-film transistors #TFT https://t.co/hL0l9OTlxi #paper


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August 07, 2018 at 10:49PM
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Aug 5, 2018

#Memristors On A Chip Solve Partial #Differential #Equations https://t.co/T2E3smdTSl #paper


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August 05, 2018 at 10:38AM
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Jul 31, 2018

Analytical #modeling of channel potential and threshold voltage of triple material gate AlGaN/GaN HEMT including trapped and polarization‐induced charges https://t.co/5pjOzA7eik https://t.co/7ibTrRWoH7 https://t.co/lXfNZLv67t


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July 31, 2018 at 09:00AM
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Analytical #modeling of channel potential and threshold voltage of triple material gate AlGaN/GaN HEMT including trapped and polarization‐induced charges https://t.co/5pjOzA7eik https://t.co/7ibTrRWoH7


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