Call for Papers for a Special Issue
of IEEE Transactions on Electron Devices
on “Reliability of CMOS Logic, Memory, Power and Beyond CMOS Devices”
Submission deadline: March 31, 2019; Publication date: October 2019
Reliability of electronic devices continues to remain as a serious issue for several technology generations. Bias Temperature Instability (BTI) continues to impact CMOS logic devices for High-K Metal Gate (HKMG) technologies, while Hot Carrier Degradation (HCD) and Self Heating Effect (SHE) have evolved as additional issues for FinFETs. The Time Dependent Dielectric Breakdown (TDDB) is still a concern and needs attention. These topics are also of interest for future devices with different channel materials (such as SiGe, Ge or III-V) and architectures (such as Gate All Around Nano Sheet FETs). The mechanisms governing degradation of program/erase window with cycling, data retention before and after cycling, etc. in conventional Vertical NAND and different emerging memories such as Resistive RAM, Phase Change RAM, Magnetic RAM and Ferroelectric RAM are of interest. Different power devices (Si and SiC FETs, IGBTs, GaN HEMTs) are becoming mainstream now and their reliability needs to be accessed. Finally, very little has been studied on the reliability of futuristic 2D channel devices.
This Special Issue of the IEEE Transactions on Electron Devices will feature the most recent developments and the state of the an in the ﬁeld of device reliability based on both experimental results and theoretical models. Papers must be new and present original material that has not been copyrighted, published or accepted for publications in any other archival publications, that is not currently being considered for publications elsewhere, and that will not be submitted elsewhere while under considerations by the Transactions on Electron Devices.
Topics of interest include, but are not limited to:
- Advanced Transistors: Negative and Positive Bias Temperature Instabilities; Hot Carrier Degradation; SelfHeating Effects; De-convolution of BTI-HCI-SHE; Variability; Random Telegraph Noise; Alternative (SiGe, Ge and III-V) channels; Novel device architectures; etc.;
- Gate Dielectrics: Charge trapping and breakdown including TDDB; Reliability of novel gate dielectrics and materials for logic and memory devices; Evaluation and modeling of progressive breakdown; Gate dielectric reliability on SiGe, Ge and III-V channels; etc.;
- Reliability of Memory Devices: DRAM and NVM including 2D and 3D NAND; Novel memory devices such as Re-RAM, Phase Change RAM, MRAM; etc.;
- Power Devices: MOSFET, HEMT, IGBT on different materials (GaN, SiC, Ga203); etc.;
- RF Devices: High frequency effects; GaN HEMT; RF 801 etc.
- Novel Devices: Negative Capacitance FETs; Ferroelectric memory FETs; Tunnel FETs; Transistors with 2D semiconductors (graphene, M082); Spintronic devices; Neuromorphic devices, etc.;
- Process-Related Reliability: Reliability issues related to different fabrication processes and layout for the above devices.
- Device-Circuit Correlation: Impact of device reliability on circuit operation including any correlation between different effects; development of compact models; circuit simulation; etc.
Submission instructions: Manuscripts should be submitted in a double column format using an IEEE style ﬁle. Please visit the following link to download the templates:
In your cover letter, please indicate that your submission is for this special issue.
Submission deadline: March 31, 2019 Publication date: October 2019
- Dr. Andreas Kerber, Globalfoundries, USA
- Dr. Chandra Mouli, Micron Technology Inc., USA
- Prof. Durga Misra, New Jersey Institute of Technology, USA
- Prof. Gaudenzio Meneghesso, University of Padova, USA
- Dr. James Stathis, IBM, USA
- Prof. Ninoslav D. Stojadinovié, University of Nis, RS
- Dr. Randy Koval, Intel, SG
- Prof. Souvik Mahapatra, Indian Institute of Technology, Bombay, IN (Guest EIC)
- Dr. Stephen Ramey, Intel, USA
- Prof Tibor Grasser, TU, Wien, A