Jan 23, 2009

A post in EDN: Simulation gets speed, capacity boost

A nice article to read. It's not very technical, but interesting anyway (may because of its not-technicallity...). I copy a paragraph:

"Spice remains only part of the simulation picture as designers add RF/wireless-communications capability to an increasing array of products. And even products that offer no RF/wireless features are exhibiting RF performance as process geometries shrink, digital speeds increase, and high-speed serial-I/O ports proliferate. Furthermore, in many cases, as frequencies rise and designers squeeze more functions into smaller and smaller spaces, chip and board design cannot occur in isolation; co-design and simulation of chip, chip package, and board must take place."

If you wish to read more (which I recommend), follow the link to EDN.

Jan 15, 2009

Papers in Solid-State Electronics

Many interesting papers in the Jan-09 issue of Solid-State Electronics:

Surface potential equation for bulk MOSFET, by G. Gildenblat, Z. Zhu, and C.C. McAndrew... (Don't miss this one... it's short, but interesting, mainly for starters)

PSP-SOI: An advanced surface potential based compact model of partially depleted SOI MOSFETs for circuit simulations, by W. Wu, X. Li, G. Gildenblat, G.O. Workman, S. Veeraraghavan, C.C. McAndrew, R. van Langevelde, G.D.J. Smit, A.J. Scholten, D.B.M. Klaassen and J. Watts... this is another must, since it's the presentation in society of the latests efforts in SOI modelling of the PSP team!