Nice papers (July, 2008)

No, we're not dead, but overworked... Here you have some nice papers, from various sources, including one which is unexpected...

A simple analytical model for the front and back gate threshold voltages of a fully-depleted asymmetric SOI MOSFET
Chung Ha Suh, Solid-State Electronics (abstract)

Analysis and Modeling of Threshold Voltage Mismatch for CMOS at 65 nm and Beyond
Jeffrey B. Johnson, Terence B. Hook, and Yoo-Mi Lee, IEEE ELECTRON DEVICE LETTERS, VOL. 29, NO. 7, JULY 20 (abstract)

An Analytical Model Based on Surface Potential for a-Si:H Thin-Film Transistors
Yuan Liu, Student Member, IEEE, Ruo-he Yao, Bin Li, Member, IEEE, and Wan-Ling Deng, JOURNAL OF DISPLAY TECHNOLOGY, VOL. 4, NO. 2, JUNE 2008 (abstract)

Papers on the IEEE TED, vol 55 (7)

Some nice papers:

An Analytical Gate Tunneling Current Model for MOSFETs Having Ultrathin Gate Oxides
Mondal, I.; Dutta, A. K.
Abstract

A Fully Three-Dimensional Atomistic Quantum Mechanical Study on Random Dopant-Induced Effects in 25-nm MOSFETs
Jiang, X.-W.; Deng, H.-X.; Luo, J.-W.; Li, S.-S.; Wang, L.-W.
Abstract

A Physical-Based PSPICE Compact Model for Poly(3-hexylthiophene) Organic Field-Effect Transistors
Meixner, R. M.; Gobel, H. H.; Qiu, H.; Ucurum, C.; Klix, W.; Stenzel, R.; Yildirim, F. A.; Bauhofer, W.; Krautschneider, W. H.
Abstract