No, we're not dead, but overworked... Here you have some nice papers, from various sources, including one which is unexpected...
A simple analytical model for the front and back gate threshold voltages of a fully-depleted asymmetric SOI MOSFET
Chung Ha Suh, Solid-State Electronics (abstract)
Analysis and Modeling of Threshold Voltage Mismatch for CMOS at 65 nm and Beyond
Jeffrey B. Johnson, Terence B. Hook, and Yoo-Mi Lee, IEEE ELECTRON DEVICE LETTERS, VOL. 29, NO. 7, JULY 20 (abstract)
An Analytical Model Based on Surface Potential for a-Si:H Thin-Film Transistors
Yuan Liu, Student Member, IEEE, Ruo-he Yao, Bin Li, Member, IEEE, and Wan-Ling Deng, JOURNAL OF DISPLAY TECHNOLOGY, VOL. 4, NO. 2, JUNE 2008 (abstract)
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