Memristor

A friend of us (Francisco J. Garcia) has pointed out a recent paper in Nature Letters (Vol 453| 1 May 2008| doi:10.1038/nature06932). I post here the abstract, because it is very interesting, though not very related to compact modeling:

Authors: Dmitri B. Strukov, Gregory S. Snider, Duncan R. Stewart & R. Stanley Williams

ABSTRACT: Anyone who ever took an electronics laboratory class will be familiar with the fundamental passive circuit elements: the resistor, the capacitor and the inductor. However, in 1971 Leon Chua reasoned from symmetry arguments that there should be a fourth fundamental element, which he called a memristor (short for memory resistor). Although he showed that such an element has many interesting and valuable circuit properties, until now no one has presented either a useful physical model or an example of a memristor.

Here we show, using a simple analytical example, that memristance arises naturally in nanoscale systems in which solid-state electronic and ionic transport are coupled under an external bias voltage. These results serve as the foundation for understanding a wide range of hysteretic current–voltage behaviour observed in many nanoscale electronic devices2–19 that involve the motion of charged atomic or molecular species, in particular certain titanium dioxide cross-point switches20–22.

There is a remarks to be done, following Francisco, since you can find a patent of a very similar device:
Genrikh et al
US Patent Application Publication No. US 2007/0200158 A1, Aug. 30, 2007
ELECTRODE STRUCTURE HAVING AT LEAST TWO OXIDE LAYERS AND NON-VOLATILE MEMORY DEVICE HAVING THE SAME
Assignee: Samsung Electronics, Co., Ltd.
Filed: Jan. 19, 2007

Process for the Selection of the Next Generation SOI MOSFET Compact Models

The Compact Modeling Council (CMC) has started the Process for the Selection of the Next Generation SOI MOSFET Compact Models.

The CMC is soliciting SOI models for both partially-depleted (PD) and dynamic depletion (DD) applications. DD refers to SOI devices which exhibit PD behavior forsome bias regions, but are fully-depleted (FD) for others.

The deadline for candidate submission is May 5 2008. CMC officers will invite a number of selected model developers to the CMC Meeting in Boston, MA on 6/5/2008.

A new selection will be done after CMC members have had time to review the presentations given by model developers.

A SOI MOSFET model recommended by CMC will make lots of money!

Who wants to compete?