Language of choice

I agree with the post from Marek Mierzwinski (below) from Tiburon Design Automation. Moreover, we people working on compact modelling should agree to use all the same language of choice. However, the nice thing about standards is having so many to choose from...

Anyway, there is a question I would like to point out: model development should be done in a language that allows easy integration with commercial simulators. Up to here, both Verilog and HDLs meet the requirements. However, the last step for a model (when it comes of age or it has been accepted by the community as the ideal model for a given device), must be to be implemented in a (many) simulator as a built-in option. In this case, obviously, implementation must be done in some lower-level language like C/C++/Fortran/etc... Otherwise, the simulator will be too sloooooowwwww to simulate large circuits.

More DG

I've been looking at a not very known journal: the International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, from Wiley. I've found an useful paper from the EKV people: "Explicit modelling of the double-gate MOSFET with VHDL-AMS". It is in the vol 19, issue 3 (may/june 2006). It seems that going VHDL is the future for all those implementing models, at least in the first stages. I agree with this trend, because it is much easier to use than trying to tie your C-code inside programs like HSPICE or Intusoft's simulator IsSpice. Moreover, it is also easier to depure and also it is easier to test the models. In some days, I should post something about model testing...

In the same issue, there is also another interesting paper about accurate substrate modelling for RF applications.