[video] How to Model a BJT Bipolar Junction Transistor

This video covers the basics of bipolar junction transistor (BJT) modeling and illustrates an easy step-by-step procedure to extract the model parameters of the popular Gummel-Poon (GP) model. While the GP model was introduced in the early 1970’s, it still enjoys a wide popularity in electronic device modeling and many modeling engineers consider it a classic and an excellent starting point for getting familiar with modeling in general.

Video Published on Aug 31, 2015

To download the project files referred to in this video visit:
http://www.keysight.com/find/eesof-how-to-model-BJT

Compact Modeling Marie Sklodowska-Curie Postdoctoral Fellowship in Spain

The European (Horizon 2020) Call for Postdoctoral Individual Marie Sklodowska-Curie Fellowships (H2020-MSCA-IF-2015) is open until September 10 2015.

I am looking for one or two candidates to work in my research group at the Universitat Rovira i Virgili (Tarragona, Spain) in the field of compact modeling of advanced semiconductor devices. Therefore, I would like to receive CVs from potential applicants. Once I have selected the candidates, we will make the application.

The candidates must have a Ph D in Electrical Engineering, Electronic Engineering, Physics, Telecommunication Engineering, or related subjects.
Candidates from all countries can apply for an Individual European Fellowship provided they have not sepent more than 12 months during the last 3 years in the country of the Host Institution (in this case, Spain)

These felowships can be for one or two years. Salaries are extremely good and the prestige of having this type of fellowship is very high. For this reason, there is a tough competition to get these fellowships.

I am looking for candidates for these Marie Curie Grants, both from Europe and outside Europe. Candidates must have a good CV (preferably with more than 4 publications as first author in international journals, in order to have chances). In order to fit the Marie Curie requirements, their age should be below 35.

If successful, the postdoctoral researchers will work on the characterization of compact modeling of any of the advanced semiconductor devices targeted by our research European projects: organic and oxide TFTs, advanced III-V HEMT and III-V MOSFETs,  SOI and Multi-Gate MOSFETs, tunnel FETs.

The specific device/s in which the postdoctoral researcher will work will depend on his/her preference and background.

Candidates must send me by e-mail (to benjamin.iniguez@gmail.com) a CV or resume by AUGUST 31 2015. Successful applicants will be informed by SEPTEMBER 2, and then we will start to make the application. The successful candidates will be informed on the steps to do.

Tarragona is a small city (110000 inhabitants) on the Mediterranean coast, about 100 Km south from Barcelona, and very well connected to Barcelona and the main Spanish cities by rail and highway. Tarragona is a very old city, very important during the Roman Empire, and with a lot of historical landmarks.

The quality of life in Tarragona is excellent. Mediterranean and mild climate the whole year. Wonderful beaches around the city (even at the city). Mountains close to the city (even the Pyrenees are not far). Besides, the city is very quiet, but with an intense nightlife.

My research group in the Department of Electronic Engineering, Universitat Rovira i Virgili (URV) is one of the strongest groups in compact modeling in Europe. We are leading one European project on compact modeling of organic and oxide TFTs (in which a total of 9 European universities and companies participate). We also participate on  other projects targeting other advanced devices.

I am looking forward to receiving excellent applications!

Benjamin IñiguezDepartment of Electronic Engineering
Tarragona, SPAIN
Universitat Rovira i Virgili (URV) 
E-mail: benjamin.iniguez@gmail.com

ESSDERC ESSCIRC in Graz (A)

 ESSDERC 2015: 45th European Solid-State Device Conference

 ESSCIRC 2015: 41th European Solid-State Circuits Conference

 September 14-18, 2015 - Graz, Austria

The aim of ESSDERC and ESSCIRC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits. The increasing level of integration for system-on-chip design made available by advances in silicon technology is, more than ever before, calling for a deeper interaction among technologists, device experts, IC designers, and system designers. While keeping separate Technical Program Committees, ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both communities. Attendees registered for either conference are encouraged to attend any of the scheduled parallel sessions, regardless to which conference they belong.

Read more:

• Program at a glance (Sept. 14 to 18, 2015 including Tutorials and Workshops)
• Program folder

[mos-ak] [Final Program] Autumn 2015 MOS-AK Workshop at ESSDERC/ESSCIRC

 Autumn 2015 MOS-AK Workshop at ESSDERC/ESSCIRC
 Graz (A) September 18, 2015
 Final Workshop Program
 <http://www.mos-ak.org/graz_2015/>

Together with the MOS-AK Workshop Scientific Program Coordinators Larry Nagel and Andrei Vladimirescu, local workshop chairs Benjamin Iniguez, URV (SP) and Jean-Michel Sallese, EPFL (CH) as well as Extended MOS-AK TPC Committee, we have pleasure to invite to the MOS-AK Workshop which will be held in Graz (A) at the ESSDERC/ESSCIRC Conference following a joint modeling session (invited talks by Prof. C.C.Enz and Prof. C.Hu) as well as a session with regular modeling paper (and the invited talk by Prof. M.Lundstrom). Next MOS-AK/Graz workshop is organized with aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors. All three modeling events would allow us to discuss all broad aspects of the compact/SPICE modeling and its Verilog-A standardization as well as highlighting important our research topics at such top level forum as the ESSCER/ESSCIRC Conferences. Already now, looking forward to meet you and all your industrial and academic partners in Graz, very soon.

Venue:   

University of Technology,
Campus Inffeldgasse
Graz (A)

Important Dates:

• Call for Papers - March 2015
• 2nd Announcement - May 2015
• Final Workshop Program - July 2015
• MOS-AK Workshop - Sept.18, 2015 <http://www.mos-ak.org/graz_2015/>
• 08:30 - 09:00 - On-site Registration
• 09:00 - 12:00 - Morning MOS-AK Session
• 12:00 - 13:00 - Lunch
• 13:00 - 16:00 - Afternoon MOS-AK Session

Postworkshop publications:
Selected best MOS-AK technical presentation will be recommended for further publication in a special issue of the International Journal of High Speed Electronics and Systems

Extended MOS-AK Committee

wg/aug/15

--
You received this message because you are subscribed to the Google Groups "mos-ak" group.
To unsubscribe from this group and stop receiving emails from it, send an email to mos-ak+unsubscribe@googlegroups.com.
To post to this group, send email to mos-ak@googlegroups.com.
Visit this group at http://groups.google.com/group/mos-ak.
For more options, visit https://groups.google.com/d/optout.

Best Practices for Compact Modeling in Verilog-A

Mcandrew, C.C.; Coram, G.J.; Gullapalli, K.K.; Jones, J.R.; Nagel, L.; Roy, A.S.; Roychowdhury, J.; Scholten, A.J.; Smit, G.D.J.; Wang, X.; Yoshitomi, S., "Best Practices for Compact Modeling in Verilog-A," Electron Devices Society, IEEE Journal of the , vol.PP, no.99, pp.1,1

doi: 10.1109/JEDS.2015.2455342

Abstract: Verilog-A is the de facto standard language that the semiconductor industry uses to define compact models. Unfortunately, it is easy to write models poorly in Verilog-A, and this can lead to unphysical model behavior, poor convergence, and difficulty in understanding and maintaining model codes. This paper details best practices for writing compact models in Verilog-A, to try to help raise the quality of compact modeling throughout the industry.

keywords: Capacitance, Computational modeling, Convergence, Hardware design languages, Integrated circuit modeling, Mathematical model, Numerical models

[read more...]

REFERENCES[1] S. Liu, K. C. Hsu, and P. Subramaniam, “ADMIT-ADVICE modeling interface tool,” Proc. IEEE Customs Integrated Circuits Conf., pp. 6.6.1- 6.6.4, 1988.
[2] M. Vlach, “Modeling and simulation with Saber,” Proc. 3rd Annual ASIC Seminar and Exhibit, pp. T11.1-T11.9, 1990.
[3] E. McReynolds, personal communication, circa 1995.
[4] E. Christen and K. Bakalar, “VHDL-AMS—A hardware description language for analog and mixed-signal applications,” IEEE Trans. Circuits and Systems II, vol. 46, no. 10, pp. 1263-1272, Oct. 1999.
[5] [Online]: http://www.accellera.org/downloads/standards/v-ams (accessed June, 2015).
[6] L. Lemaitre, G. Coram, C. McAndrew, and K. Kundert, “Extensions to Verilog-A to support compact device modeling,” Proc. IEEE Behavioral Modeling and Simulation Workshop, pp. 134-138, Oct. 2003.
[7] L. Zhou, B. P. Hu, B. Wan, and C.-J. R. Shi, “Rapid BSIM model implementation with VHDL-AMS/Verilog-AMS and MCAST compact
model compiler,” IEEE Int. SOC Conf., pp. 285-286, Sep. 2003.
[8] G. Coram and M. Ding, “Recent achievements in Verilog-A compact modeling,” MOS-AK Workshop, Dec. 2009.
[9] G. Coram, “How to (and how not to) write a compact model in Verilog- A,” Proc. IEEE Behavioral Modeling a Simulation Workshop, pp. 97-106, Oct. 2004.
[10] G. Coram and C. C. McAndrew, “Verilog-A for compact modeling: best practices for high-quality model authoring,” Workshop on Compact Modeling for RF, Sep. 2005.
[11] G. Coram, “Verilog-A: an introduction for compact modelers,” MOS-AK Workshop, Sep. 2006.
[12] M. Mierzwinski, P. O’Halloran, and B. Troyanovsky, “Developing and releasing compact models using Verilog-A,” MOS-AK Workshop, Dec. 2008.
[13] G. Depeyrot and F. Poullet, “Guidelines for Verilog-A compact model coding,” MOS-AK Workshop, Sep. 2009.
[14] M. Mierzwinski, P. O’Halloran, and B. Troyanovsky, “Practical considerations for developing, debugging, and releasing Verilog-A models,” MOS-AK Workshop, Dec. 2009.
[15] C. C. McAndrew and G. Coram, “General and junction primitives for Verilog-A compact models,” nanoHUB. doi:10.4231/D3G15TC2J, 2015.
[16] C. C. McAndrew, “R3,” nanoHUB. doi:10.4231/D3QB9V64G, 2014.
[17] L. W. Nagel, SPICE2: A Computer Program to Simulate Semiconductor Circuits, Memo. ERL-M520, Univ. California, Berkeley, May 1975.
[18] X. Li, W. Wu, G. Gildenblat, C. C. McAndrew, and A. J. Scholten, “Benchmark tests for MOSFET compact models,” in Compact Modeling: Principles, Techniques and Applications, G. Gildenblat (Ed), Springer, pp. 75-104, 2010
[19] Y. Tsividis and C. McAndrew, Operation and Modeling of the MOS Transistor, 3rd ed., New York: Oxford University Press, 2011.
[20] [Online]: http://physics.nist.gov/cuu/Constants/Citations/Search.html (accessed June, 2015)
[21] A. Parker, “Getting to the heart of the matter,” IEEE Microwave Magazine, vol. 16, no. 3, pp. 76-86, Apr. 2015. [22] H. K. Dirks, Kapazit¨atskoeffizienten nichtlinearer dissipativer Systeme, Habilitation Theses, RWTH Aachen University, 1998.
[23] A. C. T. Aarts, R. van der Hout, J. C. J. Paasschens, A. J. Scholten, M. B. Willemsen, and D. B. M. Klaassen, “New fundamental insights into capacitance modeling of laterally nonuniform MOS devices,” IEEE Trans. Electron Dev., vol. 53, no. 2, pp. 270-278, Feb. 2006.
[24] C. C. McAndrew, “Practical modeling for circuit simulation,” IEEE J. Solid-State Circuits, vol. 33, no. 3, pp. 439-448, Mar. 1998.
[25] C. C. McAndrew, “Useful numerical techniques for compact modeling,” Proc. IEEE ICMTS, pp. 121-126, Apr. 2002. [26] K. Kundert, “Hidden state in SpectreRF,” [Online]: http://http://www.designers-guide.org/analysis/hidden-state.pdf (accessed June, 2015)
[27] R. K. Johnson, The Elements of MATLAB R⃝ Style, Cambridge University Press, 2011.
[28] M. Driessen and D. B. M. Klaassen, personal communication, 2006.
[29] [Online]: https://nanohub.org/groups/needs (accessed June, 2015)
[30] L. Lemaitre, C. C. McAndrew, and S. Hamm, “ADMS-automated device model synthesizer,” Proc. IEEE CICC, pp. 27-30, May 2002.
[31] [Online]: http://sourceforge.net/projects/mot-adms/ (accessed June, 2015)

Octave-Forge Community Choice POTM

The Octave-Forge packages -- Community Choice Project of the Month for July

For one of the July "Community Choice" Projects of the Month, the community elected Octave-Forge, a central location for the collaborative development of packages for GNU Octave, a high-level interpreted language. The Octave-Forge packages expand Octave's core functionality by providing field specific features via Octave's package system. Some of the individual Octave-Forge packages include: image and signal processing, fuzzy logic, instrument control, and statistics packages.

Download Octave-Forge now.

Related Projects:

• VFreeMat--An interpreted, matrix-oriented development environment for engineering and scientific applications.
• AquaTerm--A Mac OS X grahics renderer.
• Quite Universal Circuit Simulator--A circuit simulator with graphical user interface (GUI)

Analog CMOS from 5 micrometer to 5 nanometer

 Sansen, W., "1.3 Analog CMOS from 5 micrometer to 5 nanometer," ISSCC 2015 IEEE International , vol., no., pp.1,6, 22-26 Feb. 2015 doi: 10.1109/ISSCC.2015.7062848 

Abstract: In our future, as usual, analog designers will continue to expand their expertise and knowledge in response to changing needs. While devices will change their nature and operate at higher and higher frequencies, their I-V characteristics will remain similar. In the near term, increased speed of MOS circuits, will be reached by operating deeper in weak inversion. Offset and 1/f noise will continue to play a critical role. Thus, in general, it seems that analog expertise is insensitive to technology change.

[read more]