EPFL Post-doctoral/ experienced engineer position

Candidate will integrate the Swiss CTI project CAPED for a period of 18 months. This research project aims at developing new technologies based on low power wireless communications, for communication between one intelligent pill implanted in the digestive system and an external control unit. The main industrial partner of this project is the Swiss company Motilis Medica SA. Dr. Catherine Dehollain (RF IC group leader) is the scientific coordinator of this project. 

We are looking for one post-doc/ experienced engineer specialized in low power microelectronic integrated circuits with strong practical experience in the following topics:

• Design of CMOS low power integrated circuits (analog, mixed-mode and RF blocks) 
• Design of CMOS low power integrated circuits for energy scavenging (AC to DC converter, voltage regulator, bandgap reference circuit, power-on-reset circuit, etc)
• Design of CMOS power management circuits 
• Design of CMOS low power transmitter and receiver (LNA, PLL, VCO, mixer, filters, etc) for wireless communications 
• Practical experience in the measurements of CMOS integrated circuits EDA tools dedicated to the design of integrated circuits (e.g. Cadence, Agilent ADS, Pspice, etc) 

The RF IC group provides a stimulating environment, good working conditions, and collaborations within a team of 10 researchers and PhD students working on related projects.

• Starting date: as soon as possible. 
• Contract duration: 18 months 

Application has to include a CV, copies of the diplomas, significant published or unpublished papers, motivation letter and three letters of reference (or submit 3 reference names). Please send your application at the latest at the end of February 2012 to Dr. Catherine Dehollain

C4P: 2012 IEEE Silicon Nanoelectronics Workshop

Hilton Hawaiian Village in Honolulu, Hawaii (June 10-11, 2012)
Sponsored by the IEEE Electron Device Society

Authors are encouraged to submit a full-length paper to the IEEE Transactions on Nanotechnology or the IEEE Transactions on Electron Devices. Download the Call for Papers (PDF format) Further Information The 2012 Silicon Nanoelectronics Workshop is a satellite workshop of the 2012 VLSI Symposia sponsored by the IEEE Electron Device Society. It will be held on June 10-11, 2012 at the Hilton Hawaiian Village in Honolulu, Hawaii USA. This will be the seventeenth workshop in the annual series. Original papers on nanometer-scale devices and technologies which utilize silicon or which are based on silicon substrates are welcome. Prospective authors are requested to submit an abstract in PDF format, consisting of one page of text and one page of figures. It must include the paper title, the authors’ names and affiliation(s), and the full contact information (mailing address, phone and FAX numbers, e-mail address) for the corresponding author. Accepted abstracts will be reproduced in the workshop proceedings exactly as received. Some of the accepted papers will be presented in Poster Sessions. The deadline for receipt of abstracts is 5PM (Pacific Time) April 1, 2012. Authors will be notified by April 30, 2012.

Registration forms and hotel reservation forms will be provided in the Advanced Program of the 2012 VLSI Technology Symposium (http://www.vlsisymposium.org/index.html).
Scope:
•Sub-10 nm transistors, including those employing non-classical structures, novel channel and source/drain materials, or non-thermal injection mechanisms
•Junction and insulator materials and process technology for nanoelectronic devices
•Techniques for fabrication of nanostructures, including nanometer-scale patterning
•Physics of nanoelectronic devices, e.g. quantum effects, non-equilibrium transport
•Modeling/simulation of nanoelectronic devices, e.g. including atomistic effects
•Nanoscale surface, interface, and heterojunction effects in devices
•Device scaling issues including doping fluctuations and atomic granularity
•Circuit design issues and novel circuit architectures, including quantum computing, for nanoelectronic devices
•Optoelectronics using silicon nanostructures
•Techniques targeting zero power electronics (self-supplying), including wireless sensors, energy harvesting, steep slope devices, ultra-low power design and devices
•Devices for heterogeneous integration on silicon, including Graphene, III-V devices, CNT, spin-based devices, MEMs and NEMS, etc.
[read more...]

Price per transistor on a chip

The price per transistor on a chip has dropped dramatically since Intel was founded in 1968. Some people estimate that the price of a transistor is now about the same as that of one printed newspaper character.

Intel has shipped over 200 million CPUs using high-k/metal-gate transistors – the kind used in 32nm processors -- since the technology was first put into production in November 2007. This translates to over 50,000,000,000,000,000 (50 quadrillion) transistors, or the equivalent of over 7 million transistors for every man, woman and child on earth. [more]

25th ICMTS Conference

SAN DIEGO March 19-22, 2012

Day 1	Day 2	Day 3
08:45 Registration	09:00 Registration	09:00 Registration
08:45 Welcome	09:00 Process Characterization	09:00 Matching
08:55 Design Margin	11:10 RF	10:50 Capacitance
10:45 Variability	12:10 ICMTS 2013	12:10 Closing
11:45 Exhibitor Presentation	13:50 Parameter Extraction
13:45 MEMS	16:00 Stress
15:55 Poster

Note: This program is subject to change without notice. Final printed version of program will be available at the conference.

Scientific employee, PhD student, or postdoc at TU Dresden

in circuit design 

on organic, flexible, roll-to-roll-printed & plastic-based semiconductor technologies 

The period of employment is governed by the Fixed Term Research Contracts Act (Wissenschaftszeitvertragsgesetz - WissZeitVG). The position is in the frame of the FLEXIBILITY (Flexible Multifunctional Bendable Integrated Light-Weight Ultra-Thin Systems) project funded by the EU involving 7 industry partners and 4 research institutions. PhD students will find excellence prerequisites for an innovative PhD thesis. The first wireless communication receiver fully integrated in a piece of plastic foil (without the need for a silicon chip) will be developed. The project is coordinated by our chair and provides an excellent platform for interdisciplinary cooperation with industry partners. 

Tasks: 

Design (analyses, simulation, device modelling, layout, testing and documen-tation) of circuits and systems operating up to radio frequencies in novel OLAE (Organic and Large Area Electronics) and roll-to-toll printed technologies for wireless communications. The authoring of scientific publications and the participation at project meetings and international conferences are expected. The active involvement in project management is planned for postdocs. 

Requirements:
Excellent to good master, Dipl.-Ing. or PhD degree in microelectron-ics, electrical engineering, physics or chemistry. Knowledge in circuit design, inde-pendent and flexible working attitude, innovative and analytical thinking, strong commitment, communicative team-player, good English. Knowledge in the following areas is advantageous: Integrated circuit design, OLAE, device modelling, high frequency engineering, communications and semiconductor technologies, measure-ment techniques, German language.
Miscellaneous:
Applications from women are particularly welcome. The same applies to the disabled. Interested candidates are requested to submit concise application material including CV and copy of certificates per email in pdf format to Frank.Ellinger@tu-dresden.de [read more...]

Trends confirming IEDM (by Jerzy Ruzyllo)

Fresh from IEDM, my [JR] first thought is that it continues to be a great forum to interact with people speaking the same language (language of semiconductors, that is), to refresh all contacts, and to establish new ones. And that's why people who want to stay "in touch" are drawn to the meetings such as IEDM. With at least six sessions being ran in parallel even the most diligent attendee won't be able to listen to more than some 15% of all the talks given.  So, in terms of technical contents the best source of information is a Technical Digest containing all the papers presented (which, by the way, can be acquired at the fraction of the cost of attendence at the meeting). 

Still, it is not the same as the most valuable experience come from just being there. As far as technical content is concerned my [JR] first impression is that the IEDM 2011 was mostly confirming trends in semiconductor device science and engineering that are already established rather than bringing to the surface entirely new technical solutions. 

I [JR] will be more specific in this regard in the follow up blogs. [So, stay tuned...]

Synopsys to Acquire Magma Design Automation

I copy from Synopsys site:

MOUNTAIN VIEW, Calif., Nov. 30, 2011 /PRNewswire/ -- Synopsys, Inc. (Nasdaq:SNPS), a world leader in software and IP used in the design, verification and manufacture of electronic components and systems, has signed a definitive agreement to acquire Magma® Design Automation Inc. (Nasdaq:LAVA), a provider of chip design software headquartered in San Jose, California. Bringing together complementary technology, development and support capabilities will enable the combined company to more rapidly meet customer requirements linked to chip designs at both leading-edge and mature process nodes.

Under the terms of the merger agreement, Synopsys will acquire Magma for $7.35 per Magma share in cash, resulting in a transaction value of approximately $507 million net of cash and debt acquired. The boards of directors of both companies have unanimously approved the transaction.

The closing of the merger is subject to customary conditions, including approval by the stockholders of Magma as well as U.S. regulators. In the event the merger closes as expected in the second calendar quarter of 2012, Synopsys anticipates it to be modestly accretive to non-GAAP earnings per share in its fiscal 2012. Synopsys plans to fund the acquisition with a combination of cash and debt, with the specifics to be determined at the time of close.


"The dramatic rise in complexity of today's semiconductor designs for all process nodes requires an equally dramatic increase in designer productivity. Customers are either dealing with the very complex physics of 20-nanometer design or they are squeezing the last bit of performance and cost from designs at mature, high-value nodes. To achieve success, our customers are asking for more new EDA capabilities than ever before," said Aart de Geus, chairman and CEO at Synopsys. "This acquisition will enable Synopsys to accelerate the delivery of the technology our customers need to keep the overall cost of design in check."