Joint International EUROSOI-ULIS Conference on SOI and Ultimate Integration on Silicon
Granada, Spain
on March 19-21, 2018
3rd Call for Papers
Abstract Submission Deadline: January 12, 2018
The organizing committee invites scientists and engineers working in the above fields to actively participate by submitting high quality papers. Original 2-page abstracts with illustrations will be accepted for review in pdf format. The template is available at the conference website:
congresos.ugr.es/eurosoi-ulis2018. The accepted abstracts will be published in a Proceedings book with an ISBN. The authors of the accepted contributions will be requested to provide a 4-page paper to appear in the conference proceedings, which will be submitted to the IEEE Xplore® digital library. A selection of the presented manuscripts in the conference will be invited to submit an extended version, which after a peer-review process, will be published as a Special Issue of Solid-State Electronics. A best paper award will be attributed to the best paper by the SINANO institute.
• Advanced SOI materials and wafers. Physical mechanisms and innovative SOI-like devices.
• New channel materials for CMOS: strained Si, strained SOI, SiGe, GeOI, III-V and high mobility materials on insulator; carbon nanotubes; graphene and other two-dimensional materials.
• Properties of ultra-thin films and buried oxides, defects, interface quality. Thin gate dielectrics: high-κ materials for switches and memory.
• Nanometer scale devices: technology, characterization techniques and evaluation metrics for high performance, low power, low standby power, high frequency and memory applications.
• Alternative transistor architectures including FDSOI, DGSOI, FinFET, MuGFET, vertical MOSFET, Nanowires, FeFET and Tunnel FET, MEMS/NEMS, Beyond-CMOS nanoelectronic devices.
• New functionalities in silicon-compatible nanostructures and innovative devices representing the More than Moore domain, nanoelectronic sensors, biosensor devices, energy harvesting devices, RF devices, imagers, etc.
• CMOS scaling perspectives; device/circuit level performance evaluation; switches and memory scaling. Three-dimensional integration of devices and circuits, heterogeneous integration.
• Transport phenomena, compact modeling, device simulation, front- and back-end process simulation.
• Advanced test structures and characterization techniques, parameter extraction, reliability and variability assessment techniques for new materials and novel devices.
• Emerging memory devices
Invited Speakers:• Prof. Jesús del Alamo (MIT, USA): III-V CMOS: Quo vadis?
• Prof. Hiroshi Iwai (TIT, Japan): 3D scaling of Si-IGBT.
• Prof. Enrique Calleja (Uni Madrid, Spain): MBE growth of ordered InGaN/GaN nano/microrods: basics and applications.
• Prof. Edward Yi Chang (NCTU, Taiwan): High performance GaN HEMT technologies.
• Prof. Adrian Ionescu (EPFL, Switzerland): Millivolt technology for low power digital and sensing applications.
• Dr. Byungil Kwak (SK Hynix, Korea): DRAM Peripheral Transistor Scaling using logic technologies – Future Challenges.
