Y. Xiang1,2, S. Tyaginov1,3,4, M. Vandemaele1,2, Z. Wu1,2, J. Franco1, E. Bury1, B. Truijen1, B.Parvais1,5, D. Linten1, B. Kaczer1
A BSIM-Based Predictive Hot-Carrier Aging Compact Model
4A.4; IRPS March 21- 24 2021
2Department of Electrical Engineering (ESAT), KU Leuven, Leuven (B)
3Institute for Microelectronics (IuE), TU Wien, Vienna (A)
4Ioffe Physical-Technical Institute of the Russian Academy of Sciences, Saint Petersburg (RU)
5Department of Electronics and Informatics (ETRO/VUB), Brussels (B)
Abstract: The continued challenge of front-end-of-line transistor reliability has long demanded physics-based SPICE compact models, not only for service lifetime estimation, but also for agingaware device pathfinding with technology scaling and innovation. Here, we present a predictive hot-carrier-degradation (HCD) compact model built upon the industry-standard BSIM model, that conveniently embeds the essential HCD physics within common SPICE simulation flows. We leverage and augment the established, scalable electrostatics and transport in BSIM as the input to an analytical HCD interface states generation formalism, the result of which is in turn injected back into BSIM for a selfconsistent estimation of the threshold voltage (VTH) shift and the mobility degradation. Our approach readily exhibits fundamental, non-empirical predictabilities of the stress timeand the sensing bias- dependency of transistor-level degradation, without having to resort to a priori assumptions. This will further accommodate the irregular, arbitrary voltage waveforms in transient circuit operations, thus enabling efficient evaluation of the power-performance degradation at circuit level. The model ultimately aims to lay the groundwork for a reliability-aware design-technology co-optimization in device pathfinding.
Fig: Schematic of the Pao-Sah DD current integral method used in
commercial CMs [a-e] and the extrapolated piecewise Vch(y) by
augmenting the BSIM model. In the Pao-Sah DD formalism, the actual Ids is
calculated by the difference of the integral Ξ at the source (channel potential
Vch=0) and at the “drift-diffusion limit” (at LDD, where channel potential Vch=VDS,eff), with the latter defined by velocity saturation or pinch-off. The
Vch(y) is extrapolated by using the implicit assumptions in BSIM-BULK: the
quadratic profile under gradual channel approximation (GCA) and the
hyperbolic profile under the drain-side field assumption used in substratecurrent body-effect (SCBE).
References:
[a] C. K. Dabhi. (2017). BSIM4 4.8.1 MOSFET Model: User’s Manual. [Online]. Available: https://bsim.berkeley.edu/models/bsim4/.
[b] H. Agarwal. (2017). BSIM-BULK106.2.0 MOSFET Compact Model:
Technical Manual. [Online]. Available:
https://bsim.berkeley.edu/models/bsimbulk/.
[c] S. Khandelwal. (2015). BSIM-CMG 110.0.0 Multi-Gate MOSFET
Compact Model: Technical Manual. [Online]. Available:
https://bsim.berkeley.edu/models/bsimcmg/.
[d] P. Kushwaha. (2017). BSIM-IMG 102.9.1 Independent Multi-Gate
MOSFET Compact Model: Technical Manual. [Online]. Available:
https://bsim.berkeley.edu/models/bsimimg/.
[e] W. Grabinski et al., (2019) "FOSS EKV2.6 Verilog-A Compact MOSFET
Model," ESSDERC 2019 - 49th European Solid-State Device Research
Conference (ESSDERC), Cracow, Poland, 2019, pp. 190-193, doi:
10.1109/ESSDERC.2019.8901822
[Online] Available: https://github.com/ekv26/model
