[paper] DC, LF noise and TID mechanisms in 16nm FinFETs

Stefano Bonaldo^ab, Teng Ma^ab, Serena Mattiazzo^bc, Andrea Baschirotto^de, Christian Enz^f, Daniel M.Fleetwood^g, Alessandro Paccagnella^ab, Simone Gerardin^ab

DC response, low-frequency noise, and TID-induced mechanisms in 16-nm FinFETs for high-energy physics experiments

J. NIMA Section A; available online 18 April 2022, 166727

DOI: j.nima.2022.166727

     
a University of Padova (I)
b INFN Padova (I)
c University of Padova (I)
d INFN Milano (I)
e University of Milano Bicocca (I)
f ICLab, EPFL, Lausanne (CH)
g Vanderbilt University, Nashville (USA)

Abstract: Total-ionizing-dose (TID) mechanisms are evaluated in 16nm Si bulk FinFETs at doses up to 1 Grad (SiO₂) for applications in high-energy physics experiments. The TID effects are evaluated through DC and low-frequency noise measurements by varying irradiation bias conditions, transistor channel lengths, and fin/finger layouts. The TID response of nFinFETs irradiated under positive gate bias at ultrahigh doses shows a rebound of threshold voltage with significant increase in the 1/f noise amplitude. The degradation is related to the generation of border and interface traps at the upper corners of STI oxides and at the gate oxide/channel interfaces. In contrast, pFinFETs have the worst degradation due to positive charge trapping in STI oxides, which severely degrades the device transconductance and total drain current, while negligible effects are visible in the threshold voltage and 1/f noise. The TID sensitivity depends strongly on the transistor layout. Short-channel devices have the best TID tolerance thanks to the influence of halo implantation, while pFinFETs designed with low number of fins have the worst degradation because of high densities of positive charge in the surrounding thick STI oxides. As a guideline for IC design, short-channel transistors with more than 4-fins may be preferred in order to facilitate circuit qualification.

Fig: Low-frequency noise measured at |Vds|=50mV and |Vgs|=0.85V at room temperature for pFinFET with Nfin=2 and L=16 nm, irradiated up to 1Grad (SiO2) in the ON condition

Acknowledgment: This work has been carried out within the FinFET16v2 experiment funded by the National Institute for Nuclear Physics - INFN, Italy.