[mos-ak] [online publications] Q1 2022 MOS-AK Panel

Arbeitskreis Modellierung von Systemen und Parameterextraktion

Modeling of Systems and Parameter Extraction Working Group

Q1 2022 MOS-AK Panel

Online Publications

The Extended MOS-AK Committee, has organized a very first MOS-AK Panel to discuss the FOSS EDA tools for the compact/SPICE modeling and its Verilog-A standardization and implementation. The Q1 2022 MOS-AK Panel was organized as the virtual/online event on Feb.25, 2022, with practive participation of leading FOSS EDA developers representing GnuCap, ngspice, Qucs, Xyce teams.

Online Publications:

There are MOS-AK technical presentations covering selected aspects of the compact/SPICE modeling and its Verilog-A standardization; see submitted slide presentations online at corresponding link:

https://www.mos-ak.org/panel_Q1_2022/

The MOS-AK Panelists have also contributed to FOSS EDA/Verilog-A SWOT Analysis, with selected points listed in the table below. The FOSS EDA community has a number of challenges to address, in particular, securing financial support for FOSS EDA tools developments, especially for those outside of the corporate/academic environment, is of primary concern.

The MOS-AK Association plans to continue its standardization efforts by organizing future compact modeling meetings, workshops and courses around the globe thru the Next 2022 Year, including:

• Spring MOS-AK Workshop (online) Mar/Apr 2020
• 4th MOS-AK/LAEDC Workshop, Cancun (MX) July 2022
  
• 6th Sino MOS-AK Workshop (CN), Aug. 2022
• 20th MOS-AK/ESSDERC/ESSCIRC, Milano Sept.19, 2022
• 3rd MOS-AK/India Conference, Hyderabad (IN) Postponed 2022
• 15th US MOS-AK Workshop, Silicon Valley (US) Dec. 2022
• in timeframe of IEDM and Q4 CMC Meetings

W.Grabinski on the behalf of International MOS-AK Committee

WG02032022

Table: FOSS EDA/Verilog-A SWOT Analysis

Strengths	Weaknesses
High number of potential users both in terms of EDA companies/vendors and designers High number of potential contributors once a tool as been established as "gold standard"	At least a bit financial support will be needed in the long-run
Opportunities	Challenges
A "gold standard" Verilog-A compiler, i.e. sth. Like gcc, g++ or gfortran is currently not available for Verilog-A Improve the usefulness of open-source tools dramatically Enabler for research around the world  Further improving the Verilog-A standard and enabling new modeling technologies in the long-term	Securing financial support for FOSS developments, especially for those outside of the corporate/academic environment Teamwork, between projects

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