[paper] Mobility in GC SOI Transistors

Lucas M. B. da Silva¹, Bruna Cardoso Paz², Michelly de Souza¹

Analysis of Mobility in Graded-Channel SOI Transistors Aiming at Circuit Simulation

Journal of Integrated Circuits and Systems; vol. 15, no. 2 pp.1-5 (2020) 

¹Department of Electrical Engineering, Centro Universitário FEI, São Bernardo do Campo, Brazil
²CEA, Leti, Grenoble, France

Abstract: This work presents an analysis of the behavior of the effective mobility of graded-channel FD SOI transistors using an Y-Function-based technique. Low field mobility, linear and quadratic attenuation factors were extracted from two-dimensional numerical simulations. The influence of the length of both channel regions over these parameters was analyzed. The parameters extracted from experimental data were used in a SPICE simulator, showing that it is possible to simulated GC SOI MOSFET using a regular SOI MOSFET model, by adjusting its parameters. This approach presents a percentage error smaller than 7.91% for low VDS.

Fig. Simulated curves of IDS vs. VGS and gm vs. VGS 

for GCSOI nMOSFETs with L= 2 µm and VDS=50 mV.

Acknowledgements: This study was supported by CNPq grants #311466/2016- 8 and #427975/2016-6. Authors would like to acknowledge Prof. Denis Flandre, from UCLouvain for providing the experimental samples.