Call for papers for a special issue of
IEEE Transactions on Electron Devices
"Variation aware technology and circuit codesign"
The special issue on "variation aware technology and circuit co design is devoted to the research and development activities on variation aware process device technology and co-optimization with circuit design. Rapid pace of new technology introduction to CMOS technology requires much more sophisticate optimization of process, device, and circuit design, in order to maximize return on investment. Careful optimization of process technology, device structure, layout and circuit design in holistic manner enables significant performance improvement while reducing overall power consumption with least amount of area penalty.
Among many challenges for this holistic optimization, higher process and device variation becomes one of most critical issues as process technology is marching into below 20nm node.
New material technology and non-planar device structure add additional variation source on top of conventional geometrical effect. Not only reducing extrinsic portion of variation is important understanding the effect of such variation in various actual circuit design is also very important In addition to addressing variation at individual process and design element, this special edition also touches on the impact of variation aware optimization to overall SOC design that requires both high performance and low power functional blocks.
This special edition includes, but not limited to, following topics:
- Variation reduction methods of advanced process technology, including patterning, deposition and etch processes
- Variation reduction methods of dvanced device technology, including FinFET, Nanowire, FDSOL etc.
- Co-optimization of technology and circuit to minimize variation and/orimpact of variation.
- ТCAD to understand the source of variation and provide practical method to improve.
- Novel process and device technology to cope with variation issue in coming nodes.
- SOC integration and design methodology to take process device variation into account.
BE SURE TO MENTION THE SPECIAL ISSUE WITHIN THE COVER LETTER
Submission Deadline: October 31, 2014
Scheduled Publication Date: June 2015
Stanley S.C. Song Qualcomm
Huiling Shang, IBM
Каustav Banerjee, University of California, Santa Barbara
Shuji Ikeda, TEI solution
If you have any questions about submitting a manuscript, please contact:
Jo Ann Marsh (firstname.lastname@example.org) T-ED Special Issues Administrative Support