Blog dedicated to the world of compact/SPICE modeling and its Verilog-A standardization. We are discussing the most recent developments and also a bit of history. Obviously, all comments are welcome.
Wednesday, 15 October 2014
AC and Stability Analysis in NGSPICE
The above example shows an AC analysis test-bench GSCHEM. In this example the loop is broken by R3 whose value at dc is 1mO and is changed to 1TO for ac analysis. Doing this enables NGSPICE to converge on a sensible dc operating point for open loop analysis without any imperfections such as input offset forcing the output to one of the supply rails. [read more at http://education.ingenazure.com/]