Friday, October 1, 2010

CEA-Leti Makes a R&D 20nm Fully Depleted SOI Process available through CMP

Grenoble, FRANCE, and Tokyo, JAPAN, October 1st , 2010, CEA-Leti and CMP (Circuits Multi Projets®) announced during the FDSOI Workshop at Tokyo University the launch of an Exploratory MPW (Multi Project Wafers) initiative based on FDSOI (Fully Depleted SOI) 20nm process, opening the access of its 300mm infrastructure to the design community. This MPW offer is partly supported by EUROSOI+ network that gathers the main European academic partners on SOI.

The basis of the Fully Depleted SOI 20nm technology offer will be the following:
  • CMOS transistors with an undoped channel and a silicon film thickness of 6nm
  • High-k / Metal Gate stack
  • Single threshold voltage (Vth) n- and p-MOSFET with balanced Vth of ±0.4V
  • Associated Design Kit, including SPICE model (Verilog-A language), model cards extracted from silicon data, p-cells, DRC, LVS, schematic, parasitics
  • Design Kit documentation
CMP Press Contacts:
Bernard Courtois +33 4 76 57 46 15
Kholdoun Torki +33 4 76 57 47 63

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