Ten Lessons Learned from Andy Grove [Semiwiki https://t.co/ePZ5MMBbeO] #semi https://t.co/wc8oJZVA5R
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June 26, 2021 at 12:39PM
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Jun 26, 2021
Ten Lessons Learned from Andy Grove [Semiwiki https://t.co/ePZ5MMBbeO] #semi https://t.co/wc8oJZVA5R
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Jun 25, 2021
[paper] Accelerated numerical modeling of RF circuits
Hongliang Li1, Jian-Ming Jin1, Amir Hajiaboli2, Douglas R. Jachowski2
Accelerated numerical modeling of RF circuits using network characteristic mode analysis
Int J Numer Model. 2021;e2898 pp.1-16
DOI: 10.1002/jnm.2898
2 Resonant Inc., Goleta, California, USA
Abstract: A fast numerical modeling approach based on network characteristic mode analysis (CMA) is presented and investigated for analyzing electrical layouts in miniature RF filters, such as surface acoustic wave filters. In this approach, a generalized eigenvalue decomposition is performed on the Z-parameters of an electrical layout at one or two sampling frequencies that can be computed and extracted with any numerical full-wave method. The obtained eigenvalues are used to extract modal resistance, inductance, and capacitance matrices for each eigenmode. The frequency dependence of the modal resistance matrix can be assumed a priori or determined automatically, and the modal inductance and capacitance matrices are assumed frequency independent. These modal matrices are then used to approximate the Z-parameters at any other frequencies to provide the response of the electrical layout, which can then be combined with the frequency responses of other components, such as resonators, to yield the electrical response of an entire RF filter. Compared with the previously developed analytic extension of eigenvalues, this fast CMA-based method is less affected by the frequency variation of eigenmodes since the frequency dependencies of the eigenmodes are implicitly canceled out in its formulation. The accuracy of this approach is evaluated by comparing with results from full-wave analyses. For RF circuits whose electrical sizes are small and whose frequency range of interest is relatively small, the proposed CMA- based fast frequency sweep approach is found to be sufficiently accurate and highly practical for engineering applications.
Fig: Configuration of a four-port microstrip circuit with two lumped devices
(A) Dimensions of the layout; (B) Equivalent circuit for a bandpass filter;
(C) Equivalent circuit for the Schottky diode
Acknowledgements: The third and fourth authors would like to thank Andy Guyette and Jackson Massey from Resonant, Inc. for useful discussions and help in some of the simulations presented in this article.
[paper] Nanosheet field effect transistors
J. Ajayana, D. Nirmalb, Shubham Tayala, Sandip Bhattacharyaa, L. Arivazhaganc, A.S. Augustine Fletcherb, P. Murugapandiyand, D. Ajithae
Nanosheet field effect transistors - A next generation device to keep Moore’s law alive:
An intensive study
An intensive study
Microelectronics Journal 114 (2021) 105141
DOI: 10.1016/j.mejo.2021.105141
b Karunya Institute of Technology and Sciences, Coimbatore, Tamilnadu, India
c Sri Ramakrishna Engineering College, Coimbatore, Tamilnadu, India
d Anil Neerukonda Institute of Technology & Sciences, Visakhapatnam, Andhra Pradesh, India
e Sreenidhi Institute of Science and Technology, Hyderabad, Telangana, India
Abstract: Incessant downscaling of feature size of multi-gate devices such as FinFETs and gate-all-around (GAA) nanowire (NW)-FETs leads to unadorned effects like short channel effects (SCEs) and self-heating effects (SHEs) which limits their performance and causes reliability issues. FinFET technology has resulted in a remarkable performance up to a feature size of 7nm. The research community is expecting that GAA NW-FETs will take over FinFET technology from 7nm to 5nm. However, further shrinking of feature size to 3nm will impose severe challenges to the performance of these aforesaid multi-gate devices. Subsequently, the electron device designer community needs to look for alternative device designs like nanosheet FETs (NS-FETs) to overcome the limitations of the FinFET and GAA NW-FETs technologies. The driving force behind the emergence of these NS-FETs is their ability to scale down even below a feature size of 5nm with negligible short channel effects. Therefore, in this review article we have intensively investigated the NS-FETs in terms of impact of geometrical scaling, substrate material effects, parasitic channel effects, thermal effects, compatibility with different metal gates, and source/drain (S/D) metal depth effect. Consequently, it can be concluded that vertically stacked NS-FET is the most promising solution for future digital/analog integrated circuit applications due to their outstanding capability to keep Moore’s Law alive.
Fig: 3-D views of (a) FinFET (b) stacked NW-FET (c) vertically stacked NSFET.
#Shenzhen Technology #University sets up school of #IC with Chinese #SMIC
#Shenzhen Technology #University sets up school of integrated circuit #IC with Chinese leading #chip maker #SMIC [Global Times https://t.co/qIQLPe4M1V] #semi https://t.co/49Bd3pV4dw
— Wladek Grabinski (@wladek60) Jun 25, 2021
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June 25, 2021 at 02:09PM
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Jun 23, 2021
EAI ICCASA 2021 Accepting Papers
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