[IEEE EDS Update] MIXDES 2019, Rzeszów (PL)

26th International Conference “Mixed Design of Integrated Circuits and Systems"'
MIXDES 2019 

By Marcin Janicki

On June 27–29, 2019, Rzeszów, Poland, the International Conference MIXDES 2019 took place. The event was organized by the Lodz University of Technology together with the Warsaw University of Technology. The conference was co-sponsored by Poland Section IEEE ED & CAS Societies, Polish Academy of Sciences (Section of Microelectronics and Electron Technology), and Commission of Electronics and Photonics of Polish National Committee of International Union of Radio Science—URSI. The 3-day conference program included 97 presentations from 28 countries. The following six general invited talks were presented during the conference plenary sessions:

• Advanced MOS Device Technology for Low Power Logic LSI Shinichi Takagi (The University of Tokyo, Japan)
• Quantum Bits and Quantum Computing Architecture Farzan Jazaeri (EPFL, Switzerland)
• Towards Energy-Autonomous Integrated Systems Through Ultra-low Voltage Analog IC Design Viera Stopjaková (Slovak University of Technology in Bratislava, Slovakia)
• THz Technologies and Applications Thomas Skotnicki (Institute of High Pressure Physics PAS, Poland)
• What is Killing Moore’s Law? Challenges in Advanced FinFET Technology Integration Arkadiusz Malinowski (GLOBALFOUNDRIES, USA)
• Yield and Reliability Challenges at 7nm and Below Andrzej Strojwąs (Carnegie Mellon University, USA)

The sessions also included presentations in the frame of four special sessions:

• Compact Modeling for Nanoelectronics organized by D. Tomaszewski (Institute of Electron Technology, Poland) and W. Grabiński (GMC, Switzerland)
• Intelligent Distributed Systems organized by M. Drozd (LTC Sp. z o.o., Poland), R. Sztoch, P. Sztoch (FINN Sp. z o.o., Poland), B. Sakowicz and D. Makowski (Lodz University of Technology, Poland)
• Large Scale Research Facilities organized by A. Napieralski, W. Cichalewski (Lodz University of Technology, Poland)
• Thermonuclear Fusion Projects organized by S. Simrock (ITER, France), D. Makowski (Lodz University of Technology, Poland), D. Bocian and M. Scholz (Institute of Nuclear Physics, Poland

The next MIXDES 2020 Conference will take place in Wrocław, Poland. The Preliminary Call for Papers is available at http://www.mixdes.org/downloads/call2020.pdf. More information about the past and next MIXDES Conferences can be found at http://www.mixdes.org.

Edited by Mariusz Orlikowski

MIXDES 2019 Conference Secretary

[paper] Gallium Nitride FET Model

Gallium Nitride FET Model

V V Orlov, G I Zebrev

National Research Nuclear University MEPHI, Moscow, Russia

E-mail: gizebrev@mephi.ru

Abstract: We have presented an analytical physics-based compact model of GaN power FET, which can accurately describe the I-V characteristics in all operation modes. The model considers the source-drain resistance, different interface trap densities and self-heating effects. (read more 

https://arxiv.org/ftp/arxiv/papers/1909/1909.05702.pdf)

Introduction: Gallium nitride (GaN) high electron mobility transistor (HEMT) technology has many advantages, that make it a promising candidate for high-speed power electronics. It allows high-power operation at much higher frequencies than silicon laterally diffused metal-oxide-semiconductor field-effect transistors (LDMOSFETs), currently a staple for the cellular base station industry [1]. The high breakdown voltage capability (over 100 V), high electron mobility, and high-temperature performance of GaN HEMTs are the main factors for its use in power electronics applications. Circuits design in both application regimes requires the accurate compact device models that can describe the non-linear I-V characteristics. The current state-of-the-art GaN power transistor circuit models are mostly empirical in nature and contain a large number of fitting parameters. The source-drain series resistance and self-heating make the compact modeling difficult [2]. Currently available models are not enough accurate to describe the I-V characteristics of power GaN HEMTs in all operation modes. This means, that we need a compact physics-based analytical model based on the physical description of the device. In this paper, we present a physics-based GaN power transistor model based on generic approach The paper contains 3 parts. In the first part, we will give a concise description of the model. The specific power HEMT’s effects, such as series resistance and self-heating will be discussed in the second and third parts 

[paper] Prediction of DC-AC Converter Efficiency Degradation

Kenshiro Sato, Dondee Navarro, Shinya Sekizaki, Yoshifumi Zoka, Naoto Yorino,
Hans Jürgen Mattausch, Mitiko Miura-Mattausch, 

Prediction of DC-AC Converter Efficiency Degradation due to Device Aging
Using a Compact MOSFET-Aging Model

IEICE Transactions on Electronics

論文ID 2019ECP5010, [早期公開] 公開日 2019/09/02

Online ISSN 1745-1353, Print ISSN 0916-8524, https://doi.org/10.1587/transele.2019ECP5010,
https://www.jstage.jst.go.jp/article/transele/advpub/0/advpub_2019ECP5010/_article/-char/ja,

Abstract: The degradation of a SiC-MOSFET-based DC-AC converter-circuit efficiency due to aging of the electrically active devices is investigated. The newly developed compact aging model HiSIM_HSiC for high-voltage SiC-MOSFETs is used in the investigation. The model considers explicitly the carrier-trap-density increase in the solution of the Poisson equation. Measured converter characteristics during a 3-phase line-to-ground (3LG) fault is correctly reproduced by the model. It is verified that the MOSFETs experience additional stress due to the high biases occurring during the fault event, which translates to severe MOSFET aging. Simulation results predict a 0.5% reduction of converter efficiency due to a single 70ms-3LG, which is equivalent to a year of operation under normal conditions, where no additional stress is applied. With the developed compact model, prediction of the efficiency degradation of the converter circuit under prolonged stress, for which measurements are difficult to obtain and typically not available, is also feasible.

Ph D scholarship about semiconductor device modeling in Tarragona (Spain)

We want to get one scholarship for a Ph D student position in the Department of Electronic Engineering in the Department of Electronic Engineering in the Universitat Rovira i Virgili (URV), in Tarragona , Spain. The subject of the Ph D would be o the development of new techniques of characterization and modeling of nanoscale semiconductor devices, in particular two-dimensional semiconductor devices, (which are one of the most promising device structures for downscaling to 1nm), in particular transistors or memristors. It will be related to funding research projects in which the hosting group participates.

The duration of the grant will be 3 years.

The candidate should have a  Master degree in Electrical Engineering, Electronic Engineering, Telecommunication Engineering or Physics, obtained between January 1 2020 and October  2022. A good background in Semiconductor Physics, Semiconductor Devices, or Integrated Circuit Design will be highly appreciated.

Applicants must send to my e-mail address (benjamin.iniguez@urv.cat), and by November 9 2022, a CV together witha copy of the academic certificates indicating the grades obtained for all subjects during their studies (both Bachelor Degree and Master Degree).

Tarragona is a medium city (100000 inhabitants) with a pleasant Mediterranean climate and many recreation opportunities (nice beaches, theme parks, nature preserves, mountain hiking, touristic resorts and facilities). It is located 100 km Southwest of Barcelona, and it is very well connected by train, bus, highways and even low cost flights from its own airport.

My research group in the Department of Electronic Engineering, Universitat Rovira i Virgili (URV) is one of the strongest groups in compact modeling in Europe. We have led or are leading several national and European projects targeting semiconductor device characterization, physics and modeling.

INNOVATORIUM Łukasiewicza https://t.co/Qdpl1oFlpM #paper https://t.co/5kzYx3zoVr

INNOVATORIUM Łukasiewicza https://t.co/Qdpl1oFlpM #paper pic.twitter.com/5kzYx3zoVr

— Wladek Grabinski (@wladek60) October 1, 2019

from Twitter https://twitter.com/wladek60

October 01, 2019 at 03:17PM
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Indium gallium arsenide #InGaAs one-transistor dynamic random access #1TDRAM memory https://t.co/Sog5iidjvf #paper https://t.co/A98MfTkMeI

Indium gallium arsenide #InGaAs one-transistor dynamic random access #1TDRAM memory https://t.co/Sog5iidjvf #paper pic.twitter.com/A98MfTkMeI

— Wladek Grabinski (@wladek60) October 1, 2019

from Twitter https://twitter.com/wladek60

October 01, 2019 at 01:52PM
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#GPU-Powered #SPICE: The Way Forward for #Analog #Simulation https://t.co/rfXIvQ6zS9 #paper https://t.co/M5CoIG3rIt

#GPU-Powered #SPICE: The Way Forward for #Analog #Simulation https://t.co/rfXIvQ6zS9 #paper pic.twitter.com/M5CoIG3rIt

— Wladek Grabinski (@wladek60) September 30, 2019

from Twitter https://twitter.com/wladek60

September 30, 2019 at 05:14PM
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