Jul 30, 2019

[mos-ak] Joint ESSDERC/ESSCIRC Tutorial in Krakow (PL) on Sept.23, 2019

Joint ESSDERC/ESSCIRC Tutorial: 
Nanoscale Technology – Transistor Modeling – IC Design 
Auditorium Maximum, the Jagiellonian University
Krakow (PL) on Sept.23, 2019

Together with local organization team, MOS-AK Association invites you to Joint ESSDERC/ESSCIRC Tutorial: Nanoscale Technology – Transistor Modeling – IC Design which will be organized at Auditorium Maximum of the Jagiellonian University in Krakow (PL) on Sept.23, 2019

Our joint ESSDERC/ESSCIRC Tutorial aims to provide in-depth coverage of highly relevant R&D topics by world-class experts. We will discuss and present the frontiers of electron device modeling with emphasis on the complete UT SOI development chain, reviewing the nanoscale level technologies, devices TCAD numerical simulations, thru its simulation-aware compact/SPICE modeling up to selected topics of the transistor level IC design for advanced applications. This joint tutorial is designed for academic researchers, device process engineers who are interested in device modeling; academic/industrial ICs designers (to explore RF/Analog/Mixed-Signal) and those starting in these areas as well as device fabrication, electrical characterization, modeling and parameter extraction engineers. The content will be beneficial for anyone who needs to learn what is really behind the IC fabrication and its simulation in using modern SPICE/Verilog-A device models (tutorial agenda listed below).

Joint ESSDERC/ESSCIRC Tutorial will be followed (Sept. 24-26, 2019) by four 
TRACK4: "'Compact Modeling of Devices and Circuits" Sessions with invited talk "The Synergy SPICE – Compact Models" by Prof. Andrei Vladimirescu and 11 regular conference papers (see all the details below)

Tutorial Agenda: 
8:00 – 8:30 – Registration
8:30 – 9:15 – Technology: Guillaume Besnard, SOITEC (F) – UT SOI Processing and Device Fabrication
9:15 – 10:00 – Technology: Ahmed Nejim, Silvaco Inc. (USA) – UT SOI TCAD Numerical Process/Device Simulation
10:00 – 10:30 – Coffee break
10:30 – 11:15 – Devices: Thierry Poiroux, CEA–Leti (F)  Compact modeling for FDSOI technologies: Main challenges and possible solutions
11:15 – 12:00 – Devices: Roberto Murphy, INAOE (MX) – RF Electrical Characterization
12:30 – 14:00 – Lunch
14:00 – 14:45 – Design: Christian Enz, EPFL (CH) – Systematic Design of Low-power Analog/RF CMOS Circuits using the Inversion Coefficient
14:45 -15:30 – Design: Humberto Andrade da Fonseca (Cadence, US) – Advanced SOI Design and Reliability/Ageing Simulations
15:30 – 16:00 – Coffee break
16:00 – 17:00 – Panel discussion
Venue:
Auditorium Maximum, the conference center of the Jagiellonian University
ul. Krupnicza 33, 
31-123 Kraków (PL)
Online registrations will be accepted until 20 August 2019.  
https://esscirc-essderc2019.org/how-to-register/  

On the behalf of the local organization team
Wladek Grabiński (GMC, CH)
Daniel Tomaszewski (ITE, PL)
ESSDERC/ESSCIRC
TRACK4: Compact Modeling of Devices and Circuits
https://esscirc-essderc2019.org/program/
Tuesday September 24, 2019 (14:00-15:20)

IdTimePaper Title/Location/Session
5189 14:00 -
14:26
Cryogenic MOSFET Threshold Voltage Model
Location: Seminar room
Session: Compact Modeling Under Cryogenic Conditions 
5246 14:26 -
14:53
Subthreshold Mismatch in Nanometer CMOS at Cryogenic Temperatures
Location: Seminar room
Session: Compact Modeling Under Cryogenic Conditions 
5216 14:53 -
15:20
Test Chip for Identifying Spice-Parameters of Cryogenic BiFET Circuits
Location: Seminar room
Session: Compact Modeling Under Cryogenic Conditions 
Wednesday September 25, 2019 (10:20-12:00)
IdTimePaper Title/Location/Session
5226 10:20 -
10:53
First Uni-Traveling Carrier Photodiode Compact Model Enabling Future Terahertz Communication System Design
Location: Seminar room
Session: Modeling of Compound Semiconductor Devices
5253 10:53 -
11:26
Impact of SiGe HBT Hot-Carrier Degradation on the Broadband Amplifier Output Supply Current
Location: Seminar room
Session: Modeling of Compound Semiconductor Devices 
5180 11:26 -
12:00
Monolithically Integrated GaN Power ICs Designed Using the MIT Virtual Source GaNFET (MVSG) Compact Model for Enhancement-Mode p-GaN Gate Power HEMTs, Logic Transistors and Resistors
Location: Seminar room
Session: Modeling of Compound Semiconductor Devices 
Wednesday September 25, 2019 (14:20-15:40)
IdTimePaper Title/Location/Session
5363 14:20 -
14:46
The Synergy SPICE – Compact Models
Location: Seminar room
Session: Advances in MOSFET Modeling 
5141 14:46 -
15:13
Comparison of Modeling Approaches for Transistor Degradation: Model Card Adaptations Vs Subcircuits
Location: Seminar room
Session: Advances in MOSFET Modeling 
5316 15:13 -
15:40
FOSS EKV2.6 Verilog-A Compact MOSFET Model
Location: Seminar room
Session: Advances in MOSFET Modeling 
Thursday September 26, 2019 (10:20-12:00)
IdTimePaper Title/Location/Session
5251 10:20 -
10:53
Compact Analytical Model for Trap-Related Low Frequency Noise in Junctionless Transistors
Location: Medium Aula A
Session: Modeling of Trap Effects and Noise 
5329 10:53 -
11:26
Compact Modeling of Low Frequency Noise and Thermal Noise in Junction Field Effect Transistors
Location: Medium Aula A
Session: Modeling of Trap Effects and Noise 
5239 11:26 -
12:00
Evaluation of Static/Transient Performance of TFET Inverter Regarding Device Parameters Using a Compact Model
Location: Medium Aula A
Session: Modeling of Trap Effects and Noise 
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Jul 23, 2019

#IEEE Update of the International Roadmap for Devices and Systems (#IRDS) Sets Course for Computer and Electronics Industry Growth https://t.co/WwvxXl4Sq8 #paper https://t.co/ZOwLjWV0Sr


from Twitter https://twitter.com/wladek60

July 23, 2019 at 05:31PM
via IFTTT

Looking for #Quality in #TCAD-Based Papers #IEEE #TED: “What is the definition of high quality?” In this editorial, at least partially, this question is addressed. https://t.co/c1G0YXgIdD #paper https://t.co/MbhLzUa4AZ


from Twitter https://twitter.com/wladek60

July 23, 2019 at 02:11PM
via IFTTT

#IBM gives #cancer_killing drug AI project to the #OpenSource community | ZDNet https://t.co/GdgoUmx5UT https://t.co/lfC2v7MuFP


from Twitter https://twitter.com/wladek60

July 23, 2019 at 11:34AM
via IFTTT

CODEOCEAN: Charge-Based Modeling of Long-Channel Symmetric Double-Gate Junction FETs

CODEOCEAN capsule written in OCTAVE which calculates the current and transconductances (gm, gmd and gms) using the charge based approach introduced in [1]. The capsule generates graphs demonstrating model versus TCAD simulations. The user can use the capsule code to experiment and reproduce the results in the paper [1]. 
The capsule is provided at the IEEE explorer site under the "Code&Datasets" link. https://ieeexplore.ieee.org/document/8371530 / doi: 10.1109/TED.2018.2838101 
Or at the link below https://codeocean.com/capsule/8244803/tree"

FIG: IdVg and gmVg at Vd=10mV
REF:
[1] N. Makris, F. Jazaeri, J. Sallese, R. K. Sharma and M. Bucher, "Charge-Based Modeling of Long-Channel Symmetric Double-Gate Junction FETs—Part I: Drain Current and Transconductances," in IEEE Transactions on Electron Devices, vol. 65, no. 7, pp. 2744-2750, July 2018.
doi: 10.1109/TED.2018.2838101
Abstract: The double-gate (DG) junction field-effect transistor (JFET) is a classical electron device, with a simple structure that presents many advantages in terms of not only device fabrication but also its operation. The device has been largely used in low-noise applications, but also more recently, in power electronics. Physics-based compact models for JFETs, contrary to MOSFETs, are, however, scarce. In this paper, an analytical, charge-based model is established for the mobile charges, drain current, and transconductances of symmetric DG JFETs, covering all regions of device operation. The model is unified and continuous from subthreshold to linear and saturation operation and is valid over a large temperature range. This charge-based model constitutes the basis of a full compact model of the DG JFET.
Keywords: junction gate field effect transistors;semiconductor device models;mobile charges;double-gate junction field-effect transistor;classical electron device;low-noise applications;power electronics;long-channel symmetric double-gate junction FET;symmetric DG JFET;charge-based modeling;physics-based compact models;drain current;Electric potential;JFETs;Logic gates;Integrated circuit modeling;Junctions;Mathematical model;MOSFET;Analytical model;circuit simulation;compact model;junction field-effect transistor (JFET);temperature effect