Large-Signal Static Compact Circuit #Model of SiGe Heterojunction Bipolar Phototransistors: Effect of the... https://t.co/RBNC96OpbO

Large-Signal Static Compact Circuit #Model of SiGe Heterojunction Bipolar Phototransistors: Effect of the... https://t.co/RBNC96OpbO

— Wladek Grabinski (@wladek60) February 24, 2018

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February 25, 2018 at 12:10AM
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Large-Signal Static Compact Circuit #Model of SiGe Heterojunction Bipolar Phototransistors: Effect of the Distributed Nature of Currents - IEEE Journals & Magazine https://t.co/wNNqfPzf0P

Large-Signal Static Compact Circuit #Model of SiGe Heterojunction Bipolar Phototransistors: Effect of the Distributed Nature of Currents - IEEE Journals & Magazine https://t.co/wNNqfPzf0P

— Wladek Grabinski (@wladek60) February 24, 2018

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February 25, 2018 at 12:10AM
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Extraction of Process Variation Parameters in FinFET Technology Based on Compact #Modeling and Characterization https://t.co/1RTYdSlig5

Extraction of Process Variation Parameters in FinFET Technology Based on Compact #Modeling and Characterization https://t.co/1RTYdSlig5

— Wladek Grabinski (@wladek60) February 24, 2018

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February 24, 2018 at 12:38PM
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#paper : On the Formulation of Self-heating Models for Circuit Simulation Lining Zhang, Member, IEEE, Debin... https://t.co/xKqgbSKTJs

#paper : On the Formulation of Self-heating Models for Circuit Simulation
Lining Zhang, Member, IEEE, Debin... https://t.co/xKqgbSKTJs

— Wladek Grabinski (@wladek60) February 23, 2018

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February 23, 2018 at 04:08PM
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#paper : On the Formulation of Self-heating Models for Circuit Simulation Lining Zhang, Member, IEEE, Debin Song, Ying Xiao, Xinnan Lin, Mansun Chan, Fellow, IEEE https://t.co/yNcMnQarbw

#paper : On the Formulation of Self-heating Models for Circuit Simulation
Lining Zhang, Member, IEEE, Debin Song, Ying Xiao, Xinnan Lin, Mansun Chan, Fellow, IEEE https://t.co/yNcMnQarbw

— Wladek Grabinski (@wladek60) February 23, 2018

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[Short Course] RFSOI: from basics to practical use of wireless technology

RFSOI: from basics to practical use of wireless technology

18th of March, Granada, Spain

  
Incize organizes a one-day short course at EuroSOI-ULIS about Silicon-on-Insulator (SOI) technology for RF applications. The tutorial is given by globally recognized experts in the field. It aims to provide its participants with the knowledge about SOI materials, devices, circuits and performance.

  
The Silicon-on-Insulator (SOI) technology is gaining more grounds in the domains of RF applications. Nearly 100% of RF antenna switches in wireless system Front-End Modules (FEM) are based on SOI. A FEM entirely built on SOI can be implemented in the observable future as both academia and industry are working in this direction.

  
This tutorial will be of interest for engineers and graduate students willing to prepare themselves for the future RF applications.

Program:Sunday, March 18

08:00 – 08:50	RF SOI, fabrication, materials and eco-system (Abstract)	Ionut Radu Director of Advanced R&D Soitec, France
08:50 – 09:40	Fundamentals of RF SOI technology(Abstract)	Jean-Pierre Raskin Professor UCL, Belgium
09:40 – 10:10	Break
10:10 – 11:00	22nm FDSOI Technology optimized  for RF/mmWave Applications (Abstract)	David L. Harame RF CTO Development and Enablement GlobalFoundries, Germany
11:00 – 11:50	RF SOI technology and components for 5G connectivity	Christine Raynaud Program Manager (Business Development – Technology to Design) CEA-Leti, France
11:50 – 13:30	Lunch
13:30 – 14:20	Analog and RF design on SOI (Abstract)	Barend van Liempd Senior Researcher imec, Belgium
14:20 – 15:10	Techniques and tricks for RF measurements on SOI	Andrej Rumiantsev Director RF Technologies MPI Corporation, Germany
15:10 – 15:40	Break
15:40 – 16:30	FOSS TCAD/EDA tools for advanced  SOI-device modeling (Abstract)	Wladek Grabinski R&D CM Manager MOS-AK, Switzerland
16:30 – 17:20	RF design flow for SOI	Ian Dennison Design Systems Senior Group Director Cadence, UK

To register, please use the EuroSOI-ULIS registration website

More information about the EuroSOI-ULIS conference and the technical Program

For any inquiries please email us at info@incize.com

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[paper] TFET Devices Re-Evaluation Résumé

Capturing Performance Limiting Effects in Tunnel-FETs
Michael Graef^1,2, Fabian Hosenfeld^1,2, Fabian Horst^1,2, Atieh Farokhnejad^1,2
Benjamín Iñíguez² and Alexander Kloes^1
1Competence Centre for Nanotechnology and Photonics, THM, Giessen, Germany
²DEEEA, Universitat Rovira i Virgili, Tarragona, Spain
ISTE OpenScience DOI: 10.21494/ISTE.OP.2018.0220

Abstract: In this paper a two-dimensional analytical Tunnel-FET model is revised. It is used to evaluate performance enhancing measures for the TFET regarding device geometry and physical effects. The usage of hetero-junctions is discussed and a way to suppress the ambipolar behavior of the TFET is shown. In focus of this work are the emerging variability issues with this new type of device. Random-dopant-fluctuations (rdf) have a major influence on the device performance. This effect is analyzed and compared with rdf effects in a MOSFET device. The drawn conclusions lead to a re-evaluation of performance limiting aspects of fabricated TFET devices [read more: 10.21494/ISTE.OP.2018.0220]

 FIG: a) Schematic geometry of an n-type DG Tunnel-FET, showing its structural parameters and doping profiles. b) Schematic band structure of a n-Tunnel-FET showing the different operating regimes and their dominating currents.