[Short Course] RFSOI: from basics to practical use of wireless technology

RFSOI: from basics to practical use of wireless technology

18th of March, Granada, Spain

  
Incize organizes a one-day short course at EuroSOI-ULIS about Silicon-on-Insulator (SOI) technology for RF applications. The tutorial is given by globally recognized experts in the field. It aims to provide its participants with the knowledge about SOI materials, devices, circuits and performance.

  
The Silicon-on-Insulator (SOI) technology is gaining more grounds in the domains of RF applications. Nearly 100% of RF antenna switches in wireless system Front-End Modules (FEM) are based on SOI. A FEM entirely built on SOI can be implemented in the observable future as both academia and industry are working in this direction.

  
This tutorial will be of interest for engineers and graduate students willing to prepare themselves for the future RF applications.

Program:Sunday, March 18

08:00 – 08:50	RF SOI, fabrication, materials and eco-system (Abstract)	Ionut Radu Director of Advanced R&D Soitec, France
08:50 – 09:40	Fundamentals of RF SOI technology(Abstract)	Jean-Pierre Raskin Professor UCL, Belgium
09:40 – 10:10	Break
10:10 – 11:00	22nm FDSOI Technology optimized  for RF/mmWave Applications (Abstract)	David L. Harame RF CTO Development and Enablement GlobalFoundries, Germany
11:00 – 11:50	RF SOI technology and components for 5G connectivity	Christine Raynaud Program Manager (Business Development – Technology to Design) CEA-Leti, France
11:50 – 13:30	Lunch
13:30 – 14:20	Analog and RF design on SOI (Abstract)	Barend van Liempd Senior Researcher imec, Belgium
14:20 – 15:10	Techniques and tricks for RF measurements on SOI	Andrej Rumiantsev Director RF Technologies MPI Corporation, Germany
15:10 – 15:40	Break
15:40 – 16:30	FOSS TCAD/EDA tools for advanced  SOI-device modeling (Abstract)	Wladek Grabinski R&D CM Manager MOS-AK, Switzerland
16:30 – 17:20	RF design flow for SOI	Ian Dennison Design Systems Senior Group Director Cadence, UK

To register, please use the EuroSOI-ULIS registration website

More information about the EuroSOI-ULIS conference and the technical Program

For any inquiries please email us at info@incize.com

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[paper] TFET Devices Re-Evaluation Résumé

Capturing Performance Limiting Effects in Tunnel-FETs
Michael Graef^1,2, Fabian Hosenfeld^1,2, Fabian Horst^1,2, Atieh Farokhnejad^1,2
Benjamín Iñíguez² and Alexander Kloes^1
1Competence Centre for Nanotechnology and Photonics, THM, Giessen, Germany
²DEEEA, Universitat Rovira i Virgili, Tarragona, Spain
ISTE OpenScience DOI: 10.21494/ISTE.OP.2018.0220

Abstract: In this paper a two-dimensional analytical Tunnel-FET model is revised. It is used to evaluate performance enhancing measures for the TFET regarding device geometry and physical effects. The usage of hetero-junctions is discussed and a way to suppress the ambipolar behavior of the TFET is shown. In focus of this work are the emerging variability issues with this new type of device. Random-dopant-fluctuations (rdf) have a major influence on the device performance. This effect is analyzed and compared with rdf effects in a MOSFET device. The drawn conclusions lead to a re-evaluation of performance limiting aspects of fabricated TFET devices [read more: 10.21494/ISTE.OP.2018.0220]

 FIG: a) Schematic geometry of an n-type DG Tunnel-FET, showing its structural parameters and doping profiles. b) Schematic band structure of a n-Tunnel-FET showing the different operating regimes and their dominating currents. 

[paper submission] MIXDES 2018

This year the 25th International Conference "Mixed Design of Integrated Circuits and Systems", MIXDES 2018 will take place on June 21-23, 2018 in Gdynia, Poland

Submit a paper <https://www.mixdes.org/Mixdes3/>

#NEST is a simulator for spiking neural network #model https://t.co/BZaG7UkZXD https://t.co/0yGf5g7nNJ

#NEST is a simulator for spiking neural network #model https://t.co/BZaG7UkZXD pic.twitter.com/0yGf5g7nNJ

— Wladek Grabinski (@wladek60) February 21, 2018

from Twitter https://twitter.com/wladek60

February 21, 2018 at 08:33PM
via IFTTT

[paper] Low Power Low Jitter 0.18 CMOS Ring VCO Design with Strategy Based on EKV3.0 Model

Amine AYED and Hamadi GHARIANI

LETI Laboratory-ENIS

Sfax, Tunisia

IJACSA Vol. 8, No. 12, 2017

Abstract—In this paper, the design of micro-power CMOS ring VCO with minimum jitter intended for a concept of frequency synthesizer in biotelemetry systems is studied. A design procedure implemented in MATLAB is described for a circuit realization with TSMC 0.18μm CMOS technology. This conventional design methodology based on EKV3.0 model is clearly suited to the challenges of analog circuits design with reduced channel width. Measures realized with ADS confirmed methodology capability to circuit sizing respecting the specifications of application. The designed ring VCO operates at a central frequency of 433MHz in ISM band with an amplitude of oscillation equal to 500 mV. The integration area was intrinsic (without buffers and without external capacitances). The simulated phase noise is about -108 dBc/Hz at 1MHz, the value of rms jitter is 44.8 ps and the power consumption of the designed VCO is 6.37 mW @ 433 MHz [read more...]

Fig.: Eye diagram for a VCO output @ 433MHz