A Near-Threshold Voltage Oriented Library for High-Energy Efficiency and Optimized Performance in 65nm CMOS https://t.co/OOQYhqgx9U #paper

A Near-Threshold Voltage Oriented Library for High-Energy Efficiency and Optimized Performance in 65nm CMOS https://t.co/OOQYhqgx9U #paper

— Wladek Grabinski (@wladek60) November 6, 2017

from Twitter https://twitter.com/wladek60

November 06, 2017 at 08:26PM
via IFTTT

[paper] Validation of MOSFET Model Source–Drain Symmetry

Validation of MOSFET Model Source-Drain Symmetry

Colin C. McAndrew

IEEE TED, Vol. 53, No. 9, Sep. 2006
doi: 10.1109/TED.2006.881005

Abstract: Symmetry around V_ds= 0 is a critical requirement for MOSFET models, e.g. as it affects the ability of a model to simulate distortion accurately for some RF CMOS mixers. The Gummel symmetry test (GST) has been the standard test used to evaluate the symmetry of MOSFET models. However, this test is only applicable to DC current, and is only valid when there is negligible gate or substrate current. This paper presents a DC symmetry test that is applicable in the presence of gate and substrate currents, and an AC symmetry test that is simple and effective in verifying symmetry of C_gs and C_gd.

FIG: Biasing scheme for dc symmetry testing. 

Circuit-aging #modeling based on dynamic MOSFET degradation and its verification (#SISPAD) https://t.co/QgJ5UIe7Yx

Circuit-aging #modeling based on dynamic MOSFET degradation and its verification (#SISPAD) https://t.co/QgJ5UIe7Yx

— Wladek Grabinski (@wladek60) November 2, 2017

from Twitter https://twitter.com/wladek60

November 02, 2017 at 10:43AM
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Analytical #modeling is both science and art https://t.co/DBdMqRJqkU https://t.co/G45cufzKTb

Analytical #modeling is both science and art https://t.co/DBdMqRJqkU http://pic.twitter.com/G45cufzKTb

— Wladek Grabinski (@wladek60) November 2, 2017

from Twitter https://twitter.com/wladek60

November 02, 2017 at 10:07AM
via IFTTT

#Modeling of flicker noise in quasi-ballistic FETs - IEEE Conference Publication https://t.co/JpropPaK27

#Modeling of flicker noise in quasi-ballistic FETs - IEEE Conference Publication https://t.co/JpropPaK27

— Wladek Grabinski (@wladek60) November 2, 2017

from Twitter https://twitter.com/wladek60

November 02, 2017 at 10:05AM
via IFTTT

Circuit-aging #modeling based on dynamic MOSFET degradation and its verification - IEEE Conference Publication https://t.co/QnZG525Y7R

Circuit-aging #modeling based on dynamic MOSFET degradation and its verification - IEEE Conference Publication https://t.co/QnZG525Y7R

— Wladek Grabinski (@wladek60) November 2, 2017

from Twitter https://twitter.com/wladek60

November 02, 2017 at 10:04AM
via IFTTT

[mos-ak] [2nd Announcement and Call for Papers] 10th International MOS-AK Workshop in the Silicon Valley

10th International MOS-AK Workshop

(co-located with the CMC Meeting and IEDM Conference)

http://www.mos-ak.org/silicon_valley_2017/

Silicon Valley, December 6, 2017

2nd Announcement and Call for Papers 

Together with local organization teams Cadence Design Systems and Keysight Technologies as well as International MOS-AK Board of R&D Advisers: Larry Nagel, Omega Enterprises Consulting (USA), Andrei Vladimirescu, UCB (USA); ISEP (FR) and all the Extended MOS-AK TPC Committee, we have pleasure to invite to the MOS-AK Compact Modeling Workshop which will be organized for consecutive 10th time in the timeframe of coming IEDM and CMC Meetings.

Planned,10th MOS-AK workshop organized in the Silicon Valley, aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors. 

Important Dates: 

• Call for Papers - Sept. 2017
  
• 2nd Announcement - Oct. 2017
  
• Final Workshop Program - Nov. 2017
• MOS-AK Workshop - Dec.6, 2017 

Venue: 

Cadence Design Systems 

2655 Seely Ave

San Jose, CA 95134

Building 5 (map)

Topics to be covered include the following among other related to the compact/SPICE modeling :

• Compact Modeling (CM) of the electron devices
• Advances in semiconductor technologies and processing
• Verilog-A language for CM standardization
• New CM techniques and extraction software
• Open Source TCAD/EDA modeling and simulation
• CM of passive, active, sensors and actuators
• Emerging Devices, TFT, CMOS and SOI-based memory cells
• Microwave, RF device modeling, high voltage device modeling
• Nanoscale CMOS devices and circuits
• Technology R&D, DFY, DFT and reliability/ageing IC Designs
• Foundry/Fabless Interface Strategies

Prospective authors should submit abstract online

(any related inquiries can be sent to papers@mos-ak.org)

Online Workshop Registration

(any related inquiries can be sent to register@mos-ak.org)

Postworkshop Publications:

Selected best MOS-AK technical presentation will be recommended for further publication
in a special issue of the International Journal of High Speed Electronics and Systems

Extended MOS-AK Committee

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