Call for Papers [dvconeurope] DVCon-Europe 2015

 DVCON EUROPE 2015

The Design and Verification Conference & Exhibition Europe (DVCon Europe) is the premier conference for system architects, concept engineers, software developers, design and verification engineers, and IP integrators to share the latest methodologies and technologies on the practical use of EDA and IP languages and standards used in electronic design.

The focus of this highly technical conference is on the industrial application of specialized design and verification languages such as SystemC, SystemVerilog, VHDL, UVM or e; assertions in SVA or PSL; the use of AMS languages; design automation using IP-XACT; and the use of general purpose languages C and C++.

CALL FOR PAPERS

This call for papers solicits presentations that are highly technical and reflect real life experiences in using EDA languages, standards, methodologies and tools. Industry applications of interest include (but are not limited to) automotive, mobile communication, aerospace, healthcare, chip-cards, consumer and power electronics. Submissions are encouraged in (but not restricted to) the four topic areas listed below. Low power techniques and design for functional safety (e.g., ISO 26262, DO-254) are pervasive and can be addressed in any of these topics areas.

Please submit your draft version of the paper by May 1, 2015. Detailed instructions on the paper requirements and submission process can be found on www.dvcon-europe.org. 

ESSCIRC/ESSDERC 2015 website is now active

 ESSCIRC/ESSDERC 2015 website is now active: www.esscirc-essderc2015.org

 The deadline for paper submission is 2 April, 2015.
 Looking forward to seeing you in Graz!

Prof. Wolfgang Pribyl: General Chair ESSCIRC/ESSDERC 2015
Franz Dielacher, Gernot Hueber: ESSCIRC TPC Chairs
Martin Schrems, Tibor Grasser: ESSDERC TPC Chairs

Call for Papers: [fdl7] FDL2015

 Forum on Specification & Design Languages

 [fdl7] FDL 2015 CALL FOR PAPERS

  September 14-16, 2015 | Barcelona, Spain

FDL is an international forum to exchange experiences and promote new trends in the application of languages, their associated design methods and tools for the design of electronic systems. FDL stimulates scientific and controversial discussions within and in-between scientific topics as described below. The program structure includes research working sessions, embedded tutorials, panels, and technical discussions. The Forum includes tutorials and fringe meetings, such as user group or standardization meetings. “Wild and Crazy Ideas” are also welcome.

Important Dates:

• Proposals for Special Session: March 22, 2015
• Full Research Paper submission: May 4, 2015
• Other Contributions submission: June 10, 2015
• Notification of acceptance: July 4, 2015
• Camera ready papers: August 12, 2015

[read more...]

[1st announcement] #SIXHackathon 20-21 March 2015 in Zurich (CH)

 #SIXHackathon 20-21 March 2015 in Zurich (CH)

 [1st announcement] 

Are you interested in the financial technology sector (FinTech)? Are you on the lookout for a challenge? Then take part in SIX's Hackathon in Zurich 20 - 21 March 2015 and rub shoulders with one of the financial sector's leading IT companies for 30 hours.

What you can expect
Fun, challenging questions, exciting data sets, new ideas, networking opportunities, an exchange with like-minded people; people interested in FinTech and employees from SIX who are also participating.

What you have to do
SIX will provide you with data and APIs (interface information) from FinTech. You will work in small teams. The aim is to present an expert jury with a prototype or a concept after 30 hours. You can either select a topic freely or take inspiration from one of the workshops on big data in the financial technology sector and payment solutions. You will be competing against around 100 participants.

Who is eligible to take part
In principle, any student aged over 18 at a Swiss university or university of applied science and all SIX employees are eligible to take part. Participants must have an affinity and a relevant skill-set in the areas of software development, graphic or interface design, marketing, project management or similar.

Why it’s worth to participate
You will have the opportunity to prove your skills using real-life problems and present your ideas to an expert jury. Furthermore, SIX is searching for new talents – depending on your background, successful Hackathon participants could be offered a permanent position or a traineeship at SIX.

FOR MORE INFORMATION:
http://www.six-group.com/careers/en/site/hackathon.html
REGISTER NOW:
http://www.six-group.com/careers/en/site/hackathon/registration.html

Call for Papers: ESSCIRC/ESSDERC 2015 Graz (A)

the 41st ESSCIRC and 45th ESSDERC Conferences will take place on 14 to 18 September 2015 in Graz, Austria. The event is technically co-sponsored by the IEEE Electron Device Support and the IEEE Solid-State Circuit Society.

Detailed information about the conference will soon be provided at the ESSCIRC/ESSDERC 2015 website:
www.esscirc-essderc2015.org

The deadline for paper submission is 2 April, 2015

[read more...]

FOSS GPS watch

F*watch! Why should your watch be different?

(FOSS) F*watch is an infinitely hackable GPS watch with many sensors based on a 100% Free design. Everything is free, from the PCB and watch housing design to the software stack. Moreover, only free software FOSS tools have been used during the development.

The FOSDEM2015 talk described the development process and shows a first prototype, along with performance measurements and future plans.

FOSDEM2015 Speakers:

• Federico Vaga
• Matthieu Cattin

Links: F*Watch wiki

[mos-ak] [Announcement and Call for Papers] Spring 2015 MOS-AK Workshop at DATE

 Spring 2015 MOS-AK Workshop at DATE

  Grenoble March 12, 2015

  Announcement and Call for Papers 

 

 Together with the MOS-AK Workshop Scientific Program Coordinators Larry Nagel and Andrei Vladimirescu, local workshop chairs Patrick Martin, CEA (F) and Benjamin Iniguez, URV (SP) as well as Extended MOS-AK TPC Committee, we have pleasure to invite to the Spring MOS-AK Workshop which will be held in Grenoble (F) at the DATE Conference. The event is organized with aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/Spice modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors. 

Venue:

ALPEXPO-ALPES Congres

Parc Événementiel de Grenoble

Avenue d'Innsbruck - CS 52408

38034 Grenoble cedex 2; France

Important Dates:

Call for Papers - December 2014

2nd Announcement - January 2015

Final Workshop Program - February. 2015

MOS-AK Workshop - Friday, March 12, 2015

08:30 - 09:00 - On-site Registration 

09:00 - 11:00 - Morning MOS-AK Session

11:00 - 12:00 - CM Standardization Panel

12:00 - 13:00 - Lunch

13:00 - 16:00 - Afternoon MOS-AK Session 

Topics to be covered include the following:

• Advances in semiconductor technologies and processing
  
• Compact Modeling (CM) of the electron devices
  
• Verilog-A language for CM standardization
  
• New CM techniques and extraction software
  
• Open Source TCAD/EDA modeling and simulation
  
• CM of passive, active, sensors and actuators
  
• Emerging Devices, CMOS and SOI-based memory cells
  
• Microwave, RF device modeling, high voltage device modeling
  
• Nanoscale CMOS devices and circuits
  
• Technology R&D, DFY, DFT and IC Designs
  
• Foundry/Fabless Interface Strategies

Online Abstract Submission:
Authors should submit an abstract using on-line MOS-AK submission form 

(any related inquiries can be sent to wladek@grabinski.ch)
http://www.mos-ak.org/grenoble_2015/abstracts.php

Free online workshop registration:

(any related inquiries can be sent to wladek@grabinski.ch)

http://www.mos-ak.org/grenoble_2015/registration.php

Postworkshop publications:
Selected best MOS-AK technical presentation will be recommended for further publication in a special issue of the International Journal of High Speed Electronics and Systems

Extended MOS-AK/GSA Committee

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